clk: msm: clock: Add support for early boot frequency for MSM8996

Power and perf clusters early boot up frequencies require to be
updated to maximum frequnecy of NOM voltage corner to improve
the boot up time, so add support for the same.

Change-Id: Icf54a648f47765867812edc5a68cf52b7fd58fdd
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>

Documentation/devicetree/bindings/arm/msm/clock-cpu-8996.txt

@@ -8,6 +8,7 @@ PLL FMAXes etc.
 Required properties:
 - compatible:		Must be either "qcom,cpu-clock-8996" or
 			"qcom,cpu-clock-8996-v3" or "qcom,cpu-clock-8996-pro"
+			or "qcom,cpu-clock-8996-auto"
 - reg:			Pairs of physical base addresses and region sizes of
 			memory mapped registers.
 - reg-names:		Names of the bases for the above registers. Expected
@@ -39,6 +40,11 @@ Required properties:
 			clock for the CBF.
 - cbf-dev:		The CBF cache device to which the OPP table for the
 			CBF clock domain will be added.
+
+Optional properties:
+- qcom,pwrcl-early-boot-freq:	Power cluster early boot up frequency in HZ.
+- qcom,perfcl-early-boot-freq:	Perf cluster early boot up frequency in HZ.
+
 Example:
 	clock_cpu: qcom,cpu-clock-8996@ {
 		compatible = "qcom,cpu-clock-8996";

drivers/clk/msm/clock-cpu-8996.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -1308,6 +1308,7 @@ static int cpu_clock_8996_driver_probe(struct platform_device *pdev)
 	unsigned long pwrclrate, perfclrate, cbfrate;
 	int pvs_ver = 0;
 	u32 pte_efuse;
+	u32 clk_rate;
 	char perfclspeedbinstr[] = "qcom,perfcl-speedbinXX-vXX";
 	char pwrclspeedbinstr[] = "qcom,pwrcl-speedbinXX-vXX";
 	char cbfspeedbinstr[] = "qcom,cbf-speedbinXX-vXX";
@@ -1435,6 +1436,18 @@ static int cpu_clock_8996_driver_probe(struct platform_device *pdev)
 	clk_prepare_enable(&pwrcl_alt_pll.c);
 	clk_prepare_enable(&cbf_pll.c);
 
+	/* Override the existing ealry boot frequency for power cluster */
+	ret = of_property_read_u32(pdev->dev.of_node,
+				"qcom,pwrcl-early-boot-freq", &clk_rate);
+	if (!ret)
+		pwrcl_early_boot_rate = clk_rate;
+
+	/* Override the existing ealry boot frequency for perf cluster */
+	ret = of_property_read_u32(pdev->dev.of_node,
+				"qcom,perfcl-early-boot-freq", &clk_rate);
+	if (!ret)
+		perfcl_early_boot_rate = clk_rate;
+
 	/* Set the early boot rate. This may also switch us to the ACD leg */
 	clk_set_rate(&pwrcl_clk.c, pwrcl_early_boot_rate);
 	clk_set_rate(&perfcl_clk.c, perfcl_early_boot_rate);
@@ -1450,6 +1463,7 @@ static struct of_device_id match_table[] = {
 	{ .compatible = "qcom,cpu-clock-8996" },
 	{ .compatible = "qcom,cpu-clock-8996-v3" },
 	{ .compatible = "qcom,cpu-clock-8996-pro" },
+	{ .compatible = "qcom,cpu-clock-8996-auto" },
 	{}
 };
 
@@ -1499,6 +1513,9 @@ module_exit(cpu_clock_8996_exit);
 #define HF_MUX_SEL_LF_MUX 0x1
 #define LF_MUX_SEL_ALT_PLL 0x1
 
+#define PWRCL_EARLY_BOOT_RATE 1286400000
+#define PERFCL_EARLY_BOOT_RATE 1363200000
+
 static int use_alt_pll;
 module_param(use_alt_pll, int, 0444);
 
@@ -1536,6 +1553,12 @@ int __init cpu_clock_8996_early_init(void)
 					 "qcom,cpu-clock-8996-pro")) {
 		cpu_clocks_v3 = true;
 		cpu_clocks_pro = true;
+	} else if (of_find_compatible_node(NULL, NULL,
+					"qcom,cpu-clock-8996-auto")) {
+		cpu_clocks_v3 = true;
+		cpu_clocks_pro = true;
+		pwrcl_early_boot_rate = PWRCL_EARLY_BOOT_RATE;
+		perfcl_early_boot_rate = PERFCL_EARLY_BOOT_RATE;
 	} else if (of_find_compatible_node(NULL, NULL,
 					 "qcom,cpu-clock-8996-v3")) {
 		cpu_clocks_v3 = true;