Merge "ath10k: Add copy engine register MAP for wcn3990 wlan module"
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71bbd5cfc9
4 changed files with 240 additions and 8 deletions
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@ -266,7 +266,7 @@ static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
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*/
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int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
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void *per_transfer_context,
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u32 buffer,
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dma_addr_t buffer,
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unsigned int nbytes,
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unsigned int transfer_id,
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unsigned int flags)
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@ -349,7 +349,7 @@ void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe)
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int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
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void *per_transfer_context,
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u32 buffer,
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dma_addr_t buffer,
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unsigned int nbytes,
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unsigned int transfer_id,
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unsigned int flags)
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@ -392,7 +392,8 @@ int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe)
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return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1);
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}
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int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr)
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int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
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dma_addr_t paddr)
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{
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struct ath10k *ar = pipe->ar;
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struct ath10k_ce_ring *dest_ring = pipe->dest_ring;
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@ -433,7 +434,8 @@ void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries)
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dest_ring->write_index = write_index;
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}
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int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr)
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int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
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dma_addr_t paddr)
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{
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struct ath10k *ar = pipe->ar;
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int ret;
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@ -144,7 +144,7 @@ struct ce_attr;
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*/
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int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
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void *per_transfer_send_context,
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u32 buffer,
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dma_addr_t buffer,
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unsigned int nbytes,
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/* 14 bits */
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unsigned int transfer_id,
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@ -152,7 +152,7 @@ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
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int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
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void *per_transfer_context,
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u32 buffer,
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dma_addr_t buffer,
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unsigned int nbytes,
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unsigned int transfer_id,
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unsigned int flags);
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@ -164,8 +164,10 @@ int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe);
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/*==================Recv=======================*/
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int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe);
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int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr);
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int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr);
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int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
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dma_addr_t paddr);
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int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
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dma_addr_t paddr);
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void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries);
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/* recv flags */
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@ -263,6 +265,7 @@ struct ce_attr {
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void (*recv_cb)(struct ath10k_ce_pipe *);
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};
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#ifndef CONFIG_ATH10K_SNOC
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#define SR_BA_ADDRESS 0x0000
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#define SR_SIZE_ADDRESS 0x0004
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#define DR_BA_ADDRESS 0x0008
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@ -383,6 +386,190 @@ struct ce_attr {
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#define DST_WATERMARK_HIGH_RESET 0
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#define DST_WATERMARK_ADDRESS 0x0050
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#else
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#define WCN3990_CE0_SR_BA_LOW (0x00240000)
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#define WCN3990_CE1_SR_BA_LOW (0x00241000)
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#define WCN3990_CE2_SR_BA_LOW (0x00242000)
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#define WCN3990_CE3_SR_BA_LOW (0x00243000)
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#define WCN3990_CE4_SR_BA_LOW (0x00244000)
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#define WCN3990_CE5_SR_BA_LOW (0x00245000)
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#define WCN3990_CE6_SR_BA_LOW (0x00246000)
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#define WCN3990_CE7_SR_BA_LOW (0x00247000)
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#define WCN3990_CE8_SR_BA_LOW (0x00248000)
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#define WCN3990_CE9_SR_BA_LOW (0x00249000)
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#define WCN3990_CE10_SR_BA_LOW (0x0024A000)
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#define WCN3990_CE11_SR_BA_LOW (0x0024B000)
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#define WCN3990_CE0_DR_BA_LOW (0x0024000C)
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#define WNC3990_CE0_DR_SIZE (0x00240014)
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#define WCN3990_CE0_CE_CTRL1 (0x00240018)
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#define WCN3990_CE0_HOST_IE (0x0024002C)
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#define WCN3990_CE0_HOST_IS (0x00240030)
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#define WCN3990_CE0_MISC_IE (0x00240034)
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#define WCN3990_CE0_MISC_IS (0x00240038)
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#define WCN3990_CE0_SRC_WR_INDEX (0x0024003C)
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#define WCN3990_CE0_CURRENT_SRRI (0x00240044)
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#define WCN3990_CE0_CURRENT_DRRI (0x00240048)
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#define WCN3990_CE0_SRC_WATERMARK (0x0024004C)
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#define WCN3990_CE0_DST_WATERMARK (0x00240050)
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#define WCN3990_CE0_SR_SIZE (0x00240008)
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#define HOST_IE_COPY_COMPLETE_MASK (0x00000001)
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#define WCN3990_CE_WRAPPER_HOST_INTERRUPT_SUMMARY 0x0024C000
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#define WCN3990_CE_WRAPPER_INDEX_BASE_LOW 0x0024C004
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#define WCN3990_CE_WRAPPER_INDEX_BASE_HIGH 0x0024C008
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#define CE_CTRL1_IDX_UPD_EN 0x00080000
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#define WCN3990_CE_WRAPPER_BASE_ADDRESS \
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WCN3990_CE_WRAPPER_HOST_INTERRUPT_SUMMARY
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#define WCN3990_CE0_BASE_ADDRESS \
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WCN3990_CE0_SR_BA_LOW
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#define WCN3990_CE1_BASE_ADDRESS \
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WCN3990_CE1_SR_BA_LOW
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#define WCN3990_CE2_BASE_ADDRESS \
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WCN3990_CE2_SR_BA_LOW
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#define WCN3990_CE3_BASE_ADDRESS \
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WCN3990_CE3_SR_BA_LOW
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#define WCN3990_CE4_BASE_ADDRESS \
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WCN3990_CE4_SR_BA_LOW
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#define WCN3990_CE5_BASE_ADDRESS \
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WCN3990_CE5_SR_BA_LOW
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#define WCN3990_CE6_BASE_ADDRESS \
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WCN3990_CE6_SR_BA_LOW
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#define WCN3990_CE7_BASE_ADDRESS \
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WCN3990_CE7_SR_BA_LOW
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#define WCN3990_CE8_BASE_ADDRESS \
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WCN3990_CE8_SR_BA_LOW
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#define WCN3990_CE9_BASE_ADDRESS \
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WCN3990_CE9_SR_BA_LOW
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#define WCN3990_CE10_BASE_ADDRESS \
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WCN3990_CE10_SR_BA_LOW
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#define WCN3990_CE11_BASE_ADDRESS \
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WCN3990_CE11_SR_BA_LOW
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#define SR_BA_ADDRESS (WCN3990_CE0_SR_BA_LOW\
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- WCN3990_CE0_BASE_ADDRESS)
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#define SR_SIZE_ADDRESS (WCN3990_CE0_SR_SIZE \
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- WCN3990_CE0_BASE_ADDRESS)
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#define DR_BA_ADDRESS (WCN3990_CE0_DR_BA_LOW\
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- WCN3990_CE0_BASE_ADDRESS)
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#define DR_SIZE_ADDRESS (WNC3990_CE0_DR_SIZE\
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- WCN3990_CE0_BASE_ADDRESS)
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#define WCN3990_CE_DDR_ADDRESS_FOR_RRI_LOW \
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(WCN3990_CE_WRAPPER_INDEX_BASE_LOW - WCN3990_CE_WRAPPER_BASE_ADDRESS)
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#define WCN3990_CE_DDR_ADDRESS_FOR_RRI_HIGH \
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(WCN3990_CE_WRAPPER_INDEX_BASE_HIGH - WCN3990_CE_WRAPPER_BASE_ADDRESS)
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#define CE_RRI_LOW (WCN3990_CE_WRAPPER_BASE_ADDRESS \
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+ WCN3990_CE_DDR_ADDRESS_FOR_RRI_LOW)
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#define CE_RRI_HIGH (WCN3990_CE_WRAPPER_BASE_ADDRESS \
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+ WCN3990_CE_DDR_ADDRESS_FOR_RRI_HIGH)
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 18
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 18
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00040000
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
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(((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
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CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00020000
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \
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(((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \
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CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
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(((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
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CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
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#define CE_CTRL1_DMAX_LENGTH_MSB 0
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#define CE_CTRL1_DMAX_LENGTH_LSB 0
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#define CE_CTRL1_DMAX_LENGTH_MASK 0x0000FFFF
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#define CE_CTRL1_DMAX_LENGTH_GET(x) \
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(((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB)
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#define CE_CTRL1_DMAX_LENGTH_SET(x) \
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(((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
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#define CE_CTRL1_ADDRESS (WCN3990_CE0_CE_CTRL1 \
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- WCN3990_CE0_BASE_ADDRESS)
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#define HOST_IE_ADDRESS (WCN3990_CE0_HOST_IE\
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- WCN3990_CE0_BASE_ADDRESS)
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#define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
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#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
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#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
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#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
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#define HOST_IS_COPY_COMPLETE_MASK 0x00000001
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#define HOST_IS_ADDRESS (WCN3990_CE0_HOST_IS \
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- WCN3990_CE0_BASE_ADDRESS)
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#define MISC_IE_ADDRESS (WCN3990_CE0_MISC_IE \
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- WCN3990_CE0_BASE_ADDRESS)
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#define MISC_IS_AXI_ERR_MASK 0x00000100
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#define MISC_IS_DST_ADDR_ERR_MASK 0x00000200
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#define MISC_IS_SRC_LEN_ERR_MASK 0x00000100
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#define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
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#define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
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#define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
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#define MISC_IS_ADDRESS (WCN3990_CE0_MISC_IS \
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- WCN3990_CE0_BASE_ADDRESS)
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#define SR_WR_INDEX_ADDRESS 0x3C
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#define DST_WR_INDEX_ADDRESS 0x40
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#define CURRENT_SRRI_ADDRESS (WCN3990_CE0_CURRENT_SRRI\
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- WCN3990_CE0_BASE_ADDRESS)
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#define CURRENT_DRRI_ADDRESS (WCN3990_CE0_CURRENT_DRRI\
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- WCN3990_CE0_BASE_ADDRESS)
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#define SRC_WATERMARK_LOW_MSB 0
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#define SRC_WATERMARK_LOW_LSB 16
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#define SRC_WATERMARK_LOW_MASK 0xffff0000
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#define SRC_WATERMARK_LOW_GET(x) \
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(((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)
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#define SRC_WATERMARK_LOW_SET(x) \
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(((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
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#define SRC_WATERMARK_LOW_RESET 0
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#define SRC_WATERMARK_HIGH_MSB 15
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#define SRC_WATERMARK_HIGH_LSB 0
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#define SRC_WATERMARK_HIGH_MASK 0x0000ffff
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#define SRC_WATERMARK_HIGH_GET(x) \
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(((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)
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#define SRC_WATERMARK_HIGH_SET(x) \
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(((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
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#define SRC_WATERMARK_HIGH_RESET 0
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#define SRC_WATERMARK_ADDRESS (WCN3990_CE0_SRC_WATERMARK\
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- WCN3990_CE0_BASE_ADDRESS)
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#define DST_WATERMARK_LOW_LSB 16
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#define DST_WATERMARK_LOW_MASK 0xffff0000
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#define DST_WATERMARK_LOW_SET(x) \
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(((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
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#define DST_WATERMARK_LOW_RESET 0
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#define DST_WATERMARK_HIGH_MSB 15
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#define DST_WATERMARK_HIGH_LSB 0
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#define DST_WATERMARK_HIGH_MASK 0x0000ffff
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#define DST_WATERMARK_HIGH_GET(x) \
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(((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)
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#define DST_WATERMARK_HIGH_SET(x) \
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(((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
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#define DST_WATERMARK_HIGH_RESET 0
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#define DST_WATERMARK_ADDRESS (WCN3990_CE0_DST_WATERMARK \
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- WCN3990_CE0_BASE_ADDRESS)
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#define BITS0_TO_31(val) ((uint32_t)((uint64_t)(val)\
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& (uint64_t)(0xFFFFFFFF)))
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#define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(val)\
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& (uint64_t)(0xF00000000)) >> 32))
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#endif
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static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
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{
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return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
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@ -138,6 +138,32 @@ const struct ath10k_hw_regs qca4019_regs = {
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.pcie_intr_clr_address = 0x00000010,
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};
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const struct ath10k_hw_regs wcn3990_regs = {
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.rtc_soc_base_address = 0x00000000,
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.rtc_wmac_base_address = 0x00000000,
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.soc_core_base_address = 0x00000000,
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.ce_wrapper_base_address = 0x0024C000,
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.soc_global_reset_address = 0x00000008,
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.ce0_base_address = 0x00240000,
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.ce1_base_address = 0x00241000,
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.ce2_base_address = 0x00242000,
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.ce3_base_address = 0x00243000,
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.ce4_base_address = 0x00244000,
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.ce5_base_address = 0x00245000,
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.ce6_base_address = 0x00246000,
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.ce7_base_address = 0x00247000,
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.ce8_base_address = 0x00248000,
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.ce9_base_address = 0x00249000,
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.ce10_base_address = 0x0024A000,
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.ce11_base_address = 0x0024B000,
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.soc_chip_id_address = 0x000000f0,
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.soc_reset_control_si0_rst_mask = 0x00000001,
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.soc_reset_control_ce_rst_mask = 0x00000100,
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.ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
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.ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
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.pcie_intr_fw_mask = 0x00100000,
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};
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const struct ath10k_hw_values qca988x_values = {
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.rtc_state_val_on = 3,
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.ce_count = 8,
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@ -181,6 +207,15 @@ const struct ath10k_hw_values qca4019_values = {
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.ce_desc_meta_data_lsb = 4,
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};
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const struct ath10k_hw_values wcn3990_values = {
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.rtc_state_val_on = 5,
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.ce_count = 12,
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.msi_assign_ce_max = 12,
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.num_target_ce_config_wlan = 12,
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.ce_desc_meta_data_mask = 0xFFF0,
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.ce_desc_meta_data_lsb = 4,
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};
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void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
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{
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@ -231,6 +231,7 @@ struct ath10k_hw_regs {
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u32 rtc_soc_base_address;
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u32 rtc_wmac_base_address;
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u32 soc_core_base_address;
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u32 soc_global_reset_address;
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u32 ce_wrapper_base_address;
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u32 ce0_base_address;
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u32 ce1_base_address;
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@ -240,6 +241,10 @@ struct ath10k_hw_regs {
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u32 ce5_base_address;
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u32 ce6_base_address;
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u32 ce7_base_address;
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u32 ce8_base_address;
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u32 ce9_base_address;
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u32 ce10_base_address;
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u32 ce11_base_address;
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u32 soc_reset_control_si0_rst_mask;
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u32 soc_reset_control_ce_rst_mask;
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u32 soc_chip_id_address;
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@ -257,6 +262,7 @@ extern const struct ath10k_hw_regs qca988x_regs;
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extern const struct ath10k_hw_regs qca6174_regs;
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extern const struct ath10k_hw_regs qca99x0_regs;
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extern const struct ath10k_hw_regs qca4019_regs;
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||||
extern const struct ath10k_hw_regs wcn3990_regs;
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||||
|
||||
struct ath10k_hw_values {
|
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u32 rtc_state_val_on;
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|
@ -272,6 +278,7 @@ extern const struct ath10k_hw_values qca6174_values;
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extern const struct ath10k_hw_values qca99x0_values;
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||||
extern const struct ath10k_hw_values qca9888_values;
|
||||
extern const struct ath10k_hw_values qca4019_values;
|
||||
extern const struct ath10k_hw_values wcn3990_values;
|
||||
|
||||
void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
|
||||
u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
|
||||
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|
@ -284,6 +291,7 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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#define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
|
||||
#define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
|
||||
#define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
|
||||
#define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
|
||||
|
||||
/* Known peculiarities:
|
||||
* - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue