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ARM: STi: DT: Add STiH407 family tsin1 pinctrl configuration

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tsin1 channel can be configured for either serial or parallel data
transfer. This patch adds the pinctrl config for both possibilities.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This commit is contained in:
Peter Griffin 2015-06-10 16:03:00 +02:00 • committed by Maxime Coquelin
parent 747d7e6e4c
commit 71cae849b9
1 changed files with 28 additions and 0 deletions
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28
arch/arm/boot/dts/stih407-pinctrl.dtsi
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@ -467,6 +467,34 @@
}; };
}; };
}; };
tsin1 {
pinctrl_tsin1_parallel: tsin1_parallel {
st,pins {
DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
};
};
pinctrl_tsin1_serial: tsin1_serial {
st,pins {
DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
};
};
};
}; };
pin-controller-front1 { pin-controller-front1 {