evie/android_kernel_oneplus_msm8998
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drm/i915: disable DIP while changing the port

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The register specification says we need to do this.

V2: Only write the register if the port is enabled.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni 2012-05-28 16:42:54 -03:00 • committed by Daniel Vetter
parent 0dd87d2084
commit 72b78c9d19
1 changed files with 25 additions and 7 deletions
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32
drivers/gpu/drm/i915/intel_hdmi.c
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@ -317,6 +317,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
u32 reg = VIDEO_DIP_CTL; u32 reg = VIDEO_DIP_CTL;
u32 val = I915_READ(reg); u32 val = I915_READ(reg);
u32 port;
/* If the registers were not initialized yet, they might be zeroes, /* If the registers were not initialized yet, they might be zeroes,
* which means we're selecting the AVI DIP and we're setting its * which means we're selecting the AVI DIP and we're setting its
@ -337,18 +338,26 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
return; return;
} }
val &= ~VIDEO_DIP_PORT_MASK;
switch (intel_hdmi->sdvox_reg) { switch (intel_hdmi->sdvox_reg) {
case SDVOB: case SDVOB:
val |= VIDEO_DIP_PORT_B; port = VIDEO_DIP_PORT_B;
break; break;
case SDVOC: case SDVOC:
val |= VIDEO_DIP_PORT_C; port = VIDEO_DIP_PORT_C;
break; break;
default: default:
return; return;
} }
if (port != (val & VIDEO_DIP_PORT_MASK)) {
if (val & VIDEO_DIP_ENABLE) {
val &= ~VIDEO_DIP_ENABLE;
I915_WRITE(reg, val);
}
val &= ~VIDEO_DIP_PORT_MASK;
val |= port;
}
val |= VIDEO_DIP_ENABLE; val |= VIDEO_DIP_ENABLE;
val &= ~VIDEO_DIP_ENABLE_VENDOR; val &= ~VIDEO_DIP_ENABLE_VENDOR;
@ -366,6 +375,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
u32 val = I915_READ(reg); u32 val = I915_READ(reg);
u32 port;
/* See the big comment in g4x_set_infoframes() */ /* See the big comment in g4x_set_infoframes() */
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
@ -378,21 +388,29 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
return; return;
} }
val &= ~VIDEO_DIP_PORT_MASK;
switch (intel_hdmi->sdvox_reg) { switch (intel_hdmi->sdvox_reg) {
case HDMIB: case HDMIB:
val |= VIDEO_DIP_PORT_B; port = VIDEO_DIP_PORT_B;
break; break;
case HDMIC: case HDMIC:
val |= VIDEO_DIP_PORT_C; port = VIDEO_DIP_PORT_C;
break; break;
case HDMID: case HDMID:
val |= VIDEO_DIP_PORT_D; port = VIDEO_DIP_PORT_D;
break; break;
default: default:
return; return;
} }
if (port != (val & VIDEO_DIP_PORT_MASK)) {
if (val & VIDEO_DIP_ENABLE) {
val &= ~VIDEO_DIP_ENABLE;
I915_WRITE(reg, val);
}
val &= ~VIDEO_DIP_PORT_MASK;
val |= port;
}
val |= VIDEO_DIP_ENABLE; val |= VIDEO_DIP_ENABLE;
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
VIDEO_DIP_ENABLE_GCP); VIDEO_DIP_ENABLE_GCP);