From 72cdcba92660ef04b2bcee5b449d6a245b19b33d Mon Sep 17 00:00:00 2001 From: Padmanabhan Komanduru Date: Fri, 23 Jun 2017 17:08:13 +0530 Subject: [PATCH] mdss: dp: fix the NVID parameter calculation for Display Port The NVID programming for Display Port needs to be set to twice the 'n' divider of the pixel clock RCG for 5.4 GHz link rate. Add change to take care of this in Display Port driver. Change-Id: Ied31f67372d9738e96d1d908acd96a02b82d4630 Signed-off-by: Padmanabhan Komanduru --- drivers/video/fbdev/msm/mdss_dp_util.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/video/fbdev/msm/mdss_dp_util.c b/drivers/video/fbdev/msm/mdss_dp_util.c index f7b3d4664e86..037741df4382 100644 --- a/drivers/video/fbdev/msm/mdss_dp_util.c +++ b/drivers/video/fbdev/msm/mdss_dp_util.c @@ -835,6 +835,8 @@ void mdss_dp_sw_config_msa(struct mdss_dp_drv_pdata *dp) pr_debug("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n); mvid = (pixel_m & 0xFFFF) * 5; nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF); + if (dp->link_rate == DP_LINK_RATE_540) + nvid *= 2; } pr_debug("mvid=0x%x, nvid=0x%x\n", mvid, nvid);