ASoC: fsl_esai: Add indentation for binding doc to increase readability
This patch simply adds indentations for DT binding doc to increase readability without changing any contents. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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1 changed files with 23 additions and 21 deletions
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@ -23,21 +23,23 @@ Required properties:
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- clock-names : Includes the following entries:
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- clock-names : Includes the following entries:
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"core" The core clock used to access registers
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"core" The core clock used to access registers
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"extal" The esai baud clock for esai controller used to derive
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"extal" The esai baud clock for esai controller used to
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HCK, SCK and FS.
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derive HCK, SCK and FS.
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"fsys" The system clock derived from ahb clock used to derive
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"fsys" The system clock derived from ahb clock used to
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HCK, SCK and FS.
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derive HCK, SCK and FS.
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- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
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- fsl,fifo-depth : The number of elements in the transmit and receive
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This number is the maximum allowed value for TFCR[TFWM] or RFCR[RFWM].
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FIFOs. This number is the maximum allowed value for
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TFCR[TFWM] or RFCR[RFWM].
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- fsl,esai-synchronous: This is a boolean property. If present, indicating
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- fsl,esai-synchronous: This is a boolean property. If present, indicating
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that ESAI would work in the synchronous mode, which means all the settings
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that ESAI would work in the synchronous mode, which
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for Receiving would be duplicated from Transmition related registers.
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means all the settings for Receiving would be
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duplicated from Transmition related registers.
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- big-endian : If this property is absent, the native endian mode will
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- big-endian : If this property is absent, the native endian mode
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be in use as default, or the big endian mode will be in use for all the
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will be in use as default, or the big endian mode
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device registers.
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will be in use for all the device registers.
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Example:
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Example:
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