x86: ticket spin locks: reduce instruction dependencies
Reduce the amount of partial register accesses in the NR_CPUS < 256 case, and slightly weaken resource dependencies in the other case. Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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1 changed files with 7 additions and 7 deletions
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@ -21,8 +21,10 @@
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#ifdef CONFIG_X86_32
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#ifdef CONFIG_X86_32
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# define LOCK_PTR_REG "a"
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# define LOCK_PTR_REG "a"
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# define REG_PTR_MODE "k"
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#else
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#else
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# define LOCK_PTR_REG "D"
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# define LOCK_PTR_REG "D"
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# define REG_PTR_MODE "q"
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#endif
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#endif
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#if defined(CONFIG_X86_32) && \
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#if defined(CONFIG_X86_32) && \
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@ -77,19 +79,17 @@ static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
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static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
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static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
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{
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{
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int tmp;
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int tmp, new;
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short new;
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asm volatile("movw %2,%w0\n\t"
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asm volatile("movzwl %2, %0\n\t"
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"cmpb %h0,%b0\n\t"
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"cmpb %h0,%b0\n\t"
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"leal 0x100(%" REG_PTR_MODE "0), %1\n\t"
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"jne 1f\n\t"
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"jne 1f\n\t"
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"movw %w0,%w1\n\t"
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"incb %h1\n\t"
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LOCK_PREFIX "cmpxchgw %w1,%2\n\t"
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LOCK_PREFIX "cmpxchgw %w1,%2\n\t"
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"1:"
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"1:"
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"sete %b1\n\t"
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"sete %b1\n\t"
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"movzbl %b1,%0\n\t"
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"movzbl %b1,%0\n\t"
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: "=&a" (tmp), "=&Q" (new), "+m" (lock->slock)
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: "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
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:
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:
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: "memory", "cc");
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: "memory", "cc");
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@ -136,8 +136,8 @@ static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
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"movl %0,%1\n\t"
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"movl %0,%1\n\t"
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"roll $16, %0\n\t"
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"roll $16, %0\n\t"
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"cmpl %0,%1\n\t"
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"cmpl %0,%1\n\t"
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"leal 0x00010000(%" REG_PTR_MODE "0), %1\n\t"
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"jne 1f\n\t"
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"jne 1f\n\t"
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"addl $0x00010000, %1\n\t"
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LOCK_PREFIX "cmpxchgl %1,%2\n\t"
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LOCK_PREFIX "cmpxchgl %1,%2\n\t"
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"1:"
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"1:"
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"sete %b1\n\t"
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"sete %b1\n\t"
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