evie/android_kernel_oneplus_msm8998
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Merge "msm: mdss: enable pll regulator during phy on sequence"

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Linux Build Service Account 2017-01-13 17:02:59 -08:00 • committed by Gerrit - the friendly Code Review server
commit 74f63af013
2 changed files with 17 additions and 3 deletions
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9
drivers/video/fbdev/msm/mdss_hdmi_tx.c
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@ -1773,7 +1773,7 @@ static int hdmi_tx_read_edid(struct hdmi_tx_ctrl *hdmi_ctrl)
check_sum += ebuf[ndx];
if (check_sum & 0xFF) {
DEV_ERR("%s: checksome mismatch\n", __func__);
DEV_ERR("%s: checksum mismatch\n", __func__);
ret = -EINVAL;
goto end;
}
@ -2328,6 +2328,8 @@ static void hdmi_tx_update_deep_color(struct hdmi_tx_ctrl *hdmi_ctrl)
static void hdmi_tx_hpd_int_work(struct work_struct *work)
{
struct hdmi_tx_ctrl *hdmi_ctrl = NULL;
int rc = -EINVAL;
int retry = MAX_EDID_READ_RETRY;
hdmi_ctrl = container_of(work, struct hdmi_tx_ctrl, hpd_int_work);
if (!hdmi_ctrl) {
@ -2346,7 +2348,10 @@ static void hdmi_tx_hpd_int_work(struct work_struct *work)
hdmi_ctrl->hpd_state ? "CONNECT" : "DISCONNECT");
if (hdmi_ctrl->hpd_state) {
hdmi_tx_read_sink_info(hdmi_ctrl);
while (rc && retry--)
rc = hdmi_tx_read_sink_info(hdmi_ctrl);
if (!retry && rc)
pr_warn_ratelimited("%s: EDID read failed\n", __func__);
hdmi_tx_update_deep_color(hdmi_ctrl);
hdmi_tx_send_cable_notification(hdmi_ctrl, true);

11
drivers/video/fbdev/msm/msm_mdss_io_8974.c
View file

@ -947,8 +947,11 @@ static void mdss_dsi_8996_phy_power_off(
{
int ln;
void __iomem *base;
u32 data;
MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f);
/* Turn off PLL power */
data = MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0);
MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, data & ~BIT(7));
/* 4 lanes + clk lane configuration */
for (ln = 0; ln < 5; ln++) {
@ -1004,6 +1007,7 @@ static void mdss_dsi_8996_phy_power_on(
void __iomem *base;
struct mdss_dsi_phy_ctrl *pd;
char *ip;
u32 data;
pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db);
@ -1023,6 +1027,10 @@ static void mdss_dsi_8996_phy_power_on(
}
mdss_dsi_8996_phy_regulator_enable(ctrl);
/* Turn on PLL power */
data = MIPI_INP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0);
MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, data | BIT(7));
}
static void mdss_dsi_phy_power_on(
@ -1126,6 +1134,7 @@ static void mdss_dsi_8996_phy_config(struct mdss_dsi_ctrl_pdata *ctrl)
mdss_dsi_8996_pll_source_standalone(ctrl);
}
MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f);
wmb(); /* make sure registers committed */
}