ARM: dts: msm: Add jpeg, FD and CPP HW dtsi changes for msmcobalt
Add jpeg, FD and CPP HW dtsi nodes for jpeg encoder, jpeg DMA, face detection and CPP on msmcobalt. CRs-Fixed: 1001324 Change-Id: Ia62486e070310c3dccc0dc84490e5a9147ba8a56 Signed-off-by: Ashwini Rao <ashwinik@codeaurora.org>
This commit is contained in:
Ashwini Rao
Jeevan Shriram
parent
4621d9062c
commit
752fcde3d8
1 changed files with 115 additions and 16 deletions
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@ -245,22 +245,31 @@
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interrupt-names = "fd";
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smmu-vdd-supply = <&gdsc_bimc_smmu>;
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camss-vdd-supply = <&gdsc_camss_top>;
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qcom,vdd-names = "smmu-vdd", "camss-vdd";
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clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,
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<&clock_mmss clk_fd_core_clk_src>,
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vdd-supply = <&gdsc_cpp>;
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qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd";
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clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
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<&clock_mmss clk_mmss_mnoc_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
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<&clock_mmss clk_mmss_camss_ahb_clk>,
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<&clock_mmss clk_mmss_camss_top_ahb_clk>,
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<&clock_mmss clk_mmss_fd_core_clk>,
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<&clock_mmss clk_mmss_fd_core_uar_clk>,
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<&clock_mmss clk_mmss_fd_ahb_clk>,
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<&clock_mmss clk_mmss_camss_ahb_clk>,
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<&clock_mmss clk_mmss_camss_cpp_axi_clk>,
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<&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>;
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clock-names = "camss_top_ahb_clk",
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"fd_core_clk_src", "fd_core_clk",
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"fd_core_uar_clk", "fd_ahb_clk",
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"camss_ahb_clk", "camss_cpp_axi_clk",
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"cpp_vbif_ahb_clk";
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qcom,clock-rates = <0 400000000 400000000>,
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<0 0 0 0 0>;
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clock-names = "mmss_mnoc_maxi_clk",
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"mmss_mnoc_ahb_clk",
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"mmss_bimc_smmu_ahb_clk",
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"mmss_bimc_smmu_axi_clk",
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"mmss_camss_ahb_clk",
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"mmss_camss_top_ahb_clk",
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"mmss_fd_core_clk",
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"mmss_fd_core_uar_clk",
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"mmss_fd_ahb_clk",
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"mmss_camss_cpp_axi_clk",
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"mmss_camss_cpp_vbif_ahb_clk";
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qcom,clock-rates = <0 0 0 0 0 0 200000000 0 0 0 0>;
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qcom,msm-bus,name = "msm_camera_fd";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <1>;
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@ -291,20 +300,24 @@
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camss-vdd-supply = <&gdsc_camss_top>;
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vdd-supply = <&gdsc_cpp>;
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qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd";
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clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,
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clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
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<&clock_mmss clk_mmss_mnoc_ahb_clk>,
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<&clock_mmss clk_mmss_camss_ahb_clk>,
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<&clock_mmss clk_mmss_camss_top_ahb_clk>,
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<&clock_mmss clk_cpp_clk_src>,
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<&clock_mmss clk_mmss_camss_cpp_ahb_clk>,
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<&clock_mmss clk_mmss_camss_cpp_axi_clk>,
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<&clock_mmss clk_mmss_camss_cpp_clk>,
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<&clock_mmss clk_mmss_camss_micro_ahb_clk>,
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<&clock_mmss clk_mmss_camss_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
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<&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>;
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clock-names = "camss_top_ahb_clk",
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clock-names = "mnoc_maxi_clk", "mnoc_ahb_clk",
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"camss_ahb_clk", "camss_top_ahb_clk",
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"cpp_core_clk", "camss_cpp_ahb_clk",
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"camss_cpp_axi_clk", "camss_cpp_clk",
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"micro_iface_clk", "camss_ahb_clk",
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"micro_iface_clk", "mmss_smmu_axi_clk",
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"cpp_vbif_ahb_clk";
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qcom,clock-rates = <0 200000000 0 0 200000000 0 0 0>;
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qcom,clock-rates = <0 0 0 0 200000000 0 0 200000000 0 0 0>;
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qcom,min-clock-rate = <200000000>;
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qcom,bus-master = <1>;
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qcom,vbif-qos-setting = <0x20 0x10000000>,
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@ -620,6 +633,92 @@
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status = "disabled";
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};
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};
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qcom,jpeg@ca1c000 {
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cell-index = <0>;
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compatible = "qcom,jpeg";
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reg = <0xca1c000 0x4000>,
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<0xca60000 0x3000>;
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reg-names = "jpeg_hw", "jpeg_vbif";
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interrupts = <0 316 0>;
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interrupt-names = "jpeg";
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smmu-vdd-supply = <&gdsc_bimc_smmu>;
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camss-vdd-supply = <&gdsc_camss_top>;
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qcom,vdd-names = "smmu-vdd", "camss-vdd";
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clock-names = "mmss_mnoc_maxi_clk",
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"mmss_mnoc_ahb_clk",
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"mmss_bimc_smmu_ahb_clk",
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"mmss_bimc_smmu_axi_clk",
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"mmss_camss_ahb_clk",
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"mmss_camss_top_ahb_clk",
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"mmss_camss_jpeg0_clk",
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"mmss_camss_jpeg_ahb_clk",
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"mmss_camss_jpeg_axi_clk";
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clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
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<&clock_mmss clk_mmss_mnoc_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
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<&clock_mmss clk_mmss_camss_ahb_clk>,
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<&clock_mmss clk_mmss_camss_top_ahb_clk>,
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<&clock_mmss clk_mmss_camss_jpeg0_clk>,
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<&clock_mmss clk_mmss_camss_jpeg_ahb_clk>,
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<&clock_mmss clk_mmss_camss_jpeg_axi_clk>;
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qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>;
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qcom,vbif-reg-settings = <0x4 0x1>;
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qcom,prefetch-reg-settings = <0x30c 0x1111>,
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<0x318 0x31>,
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<0x324 0x31>,
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<0x330 0x31>,
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<0x33c 0x0>;
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qcom,msm-bus,name = "msm_camera_jpeg0";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps = <62 512 0 0>,
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<62 512 666675 666675>;
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status = "disabled";
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};
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qcom,jpeg@caa0000 {
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cell-index = <3>;
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compatible = "qcom,jpegdma";
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reg = <0xcaa0000 0x4000>,
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<0xca60000 0x3000>;
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reg-names = "jpeg_hw", "jpeg_vbif";
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interrupts = <0 304 0>;
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interrupt-names = "jpeg";
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smmu-vdd-supply = <&gdsc_bimc_smmu>;
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camss-vdd-supply = <&gdsc_camss_top>;
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qcom,vdd-names = "smmu-vdd", "camss-vdd";
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clock-names = "mmss_mnoc_maxi_clk",
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"mmss_mnoc_ahb_clk",
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"mmss_bimc_smmu_ahb_clk",
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"mmss_bimc_smmu_axi_clk",
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"mmss_camss_ahb_clk",
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"mmss_camss_top_ahb_clk",
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"core_clk",
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"mmss_camss_jpeg_ahb_clk",
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"mmss_camss_jpeg_axi_clk";
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clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
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<&clock_mmss clk_mmss_mnoc_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
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<&clock_mmss clk_mmss_camss_ahb_clk>,
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<&clock_mmss clk_mmss_camss_top_ahb_clk>,
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<&clock_mmss clk_mmss_camss_jpeg0_clk>,
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<&clock_mmss clk_mmss_camss_jpeg_ahb_clk>,
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<&clock_mmss clk_mmss_camss_jpeg_axi_clk>;
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qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>;
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qcom,vbif-reg-settings = <0x4 0x1>;
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qcom,prefetch-reg-settings = <0x18c 0x11>,
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<0x1a0 0x31>,
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<0x1b0 0x31>;
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qcom,msm-bus,name = "msm_camera_jpeg_dma";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps = <62 512 0 0>,
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<62 512 666675 666675>;
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status = "disabled";
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};
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};
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&i2c_freq_100Khz {
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