evie/android_kernel_oneplus_msm8998
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sparc64: Fix huge PMD to PTE translation for sun4u in TLB miss handler.

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When we set the sun4u version of the PTE execute bit, it's:

	or	REG, _PAGE_EXEC_4U, REG

_PAGE_EXEC_4U is 0x1000, unfortunately the immedate field of the
'or' instruction is a signed 13-bit value.  So the above actually
assembles into:

	or	REG, -4096, REG

completely corrupting the final PTE value.

Set it with a:

	sethi	%hi(_PAGE_EXEC_4U), TMP
	or	REG, TMP, REG

sequence instead.

This fixes "git gc" crashes on sun4u machines.

Reported-by: Meelis Roos <mroos@linux.ee>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2013-02-20 12:38:40 -08:00
parent 0fbebed682
commit 76968ad2ea
1 changed files with 19 additions and 9 deletions
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28
arch/sparc/include/asm/tsb.h
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@ -157,17 +157,26 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
andn REG2, 0x7, REG2; \ andn REG2, 0x7, REG2; \
add REG1, REG2, REG1; add REG1, REG2, REG1;
/* This macro exists only to make the PMD translator below easier /* These macros exists only to make the PMD translator below
* to read. It hides the ELF section switch for the sun4v code * easier to read. It hides the ELF section switch for the
* patching. * sun4v code patching.
*/ */
#define OR_PTE_BIT(REG, NAME) \ #define OR_PTE_BIT_1INSN(REG, NAME) \
661: or REG, _PAGE_##NAME##_4U, REG; \ 661: or REG, _PAGE_##NAME##_4U, REG; \
.section .sun4v_1insn_patch, "ax"; \ .section .sun4v_1insn_patch, "ax"; \
.word 661b; \ .word 661b; \
or REG, _PAGE_##NAME##_4V, REG; \ or REG, _PAGE_##NAME##_4V, REG; \
.previous; .previous;
#define OR_PTE_BIT_2INSN(REG, TMP, NAME) \
661: sethi %hi(_PAGE_##NAME##_4U), TMP; \
or REG, TMP, REG; \
.section .sun4v_2insn_patch, "ax"; \
.word 661b; \
mov -1, TMP; \
or REG, _PAGE_##NAME##_4V, REG; \
.previous;
/* Load into REG the PTE value for VALID, CACHE, and SZHUGE. */ /* Load into REG the PTE value for VALID, CACHE, and SZHUGE. */
#define BUILD_PTE_VALID_SZHUGE_CACHE(REG) \ #define BUILD_PTE_VALID_SZHUGE_CACHE(REG) \
661: sethi %uhi(_PAGE_VALID|_PAGE_SZHUGE_4U), REG; \ 661: sethi %uhi(_PAGE_VALID|_PAGE_SZHUGE_4U), REG; \
@ -214,12 +223,13 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
andn REG1, PMD_HUGE_PROTBITS, REG2; \ andn REG1, PMD_HUGE_PROTBITS, REG2; \
sllx REG2, PMD_PADDR_SHIFT, REG2; \ sllx REG2, PMD_PADDR_SHIFT, REG2; \
/* REG2 now holds PFN << PAGE_SHIFT */ \ /* REG2 now holds PFN << PAGE_SHIFT */ \
andcc REG1, PMD_HUGE_EXEC, %g0; \ andcc REG1, PMD_HUGE_WRITE, %g0; \
bne,a,pt %xcc, 1f; \ bne,a,pt %xcc, 1f; \
OR_PTE_BIT(REG2, EXEC); \ OR_PTE_BIT_1INSN(REG2, W); \
1: andcc REG1, PMD_HUGE_WRITE, %g0; \ 1: andcc REG1, PMD_HUGE_EXEC, %g0; \
bne,a,pt %xcc, 1f; \ be,pt %xcc, 1f; \
OR_PTE_BIT(REG2, W); \ nop; \
OR_PTE_BIT_2INSN(REG2, REG1, EXEC); \
/* REG1 can now be clobbered, build final PTE */ \ /* REG1 can now be clobbered, build final PTE */ \
1: BUILD_PTE_VALID_SZHUGE_CACHE(REG1); \ 1: BUILD_PTE_VALID_SZHUGE_CACHE(REG1); \
ba,pt %xcc, PTE_LABEL; \ ba,pt %xcc, PTE_LABEL; \