[ARM] 4130/1: Add L220 support to RealView/EB

This patch enables the L220 on the RealView/EB MPCore platform.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas 2007-02-05 14:48:24 +01:00 committed by Russell King
parent 4ba9dcbeba
commit 7770bddb27
3 changed files with 14 additions and 0 deletions

View file

@ -10,6 +10,7 @@ config MACH_REALVIEW_EB
config REALVIEW_MPCORE config REALVIEW_MPCORE
bool "Support MPcore tile" bool "Support MPcore tile"
depends on MACH_REALVIEW_EB depends on MACH_REALVIEW_EB
select CACHE_L2X0
help help
Enable support for the MPCore tile on the Realview platform. Enable support for the MPCore tile on the Realview platform.
Since there are device address and interrupt differences, a Since there are device address and interrupt differences, a

View file

@ -31,6 +31,7 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/hardware/gic.h> #include <asm/hardware/gic.h>
#include <asm/hardware/icst307.h> #include <asm/hardware/icst307.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
@ -69,6 +70,11 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
.pfn = __phys_to_pfn(REALVIEW_GIC1_DIST_BASE), .pfn = __phys_to_pfn(REALVIEW_GIC1_DIST_BASE),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_MPCORE_L220_BASE),
.pfn = __phys_to_pfn(REALVIEW_MPCORE_L220_BASE),
.length = SZ_8K,
.type = MT_DEVICE,
}, },
#endif #endif
{ {
@ -170,6 +176,11 @@ static void __init realview_eb_init(void)
{ {
int i; int i;
#ifdef CONFIG_REALVIEW_MPCORE
/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
* Bits: .... ...0 0111 1001 0000 .... .... .... */
l2x0_init(__io_address(REALVIEW_MPCORE_L220_BASE), 0x00790000, 0xfe000fff);
#endif
clk_register(&realview_clcd_clk); clk_register(&realview_clcd_clk);
platform_device_register(&realview_flash_device); platform_device_register(&realview_flash_device);

View file

@ -213,6 +213,7 @@
#define REALVIEW_TWD_BASE 0x10100700 #define REALVIEW_TWD_BASE 0x10100700
#define REALVIEW_TWD_SIZE 0x00000100 #define REALVIEW_TWD_SIZE 0x00000100
#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ #define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */
#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ #define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
#else #else
#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */ #define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
@ -220,6 +221,7 @@
#define REALVIEW_TWD_BASE 0x1F000700 #define REALVIEW_TWD_BASE 0x1F000700
#define REALVIEW_TWD_SIZE 0x00000100 #define REALVIEW_TWD_SIZE 0x00000100
#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ #define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */
#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ #define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
#endif #endif
#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ #define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */