From 77fd5db7ee660916f6909a6e004e70e61a4bf5fe Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 17 May 2016 15:26:33 -0600 Subject: [PATCH] ARM: dts: msm: Add LMH DCVSh interrupt information for msmcobalt Add information about the interrupt generated by the LMH DCVSh block for msmcobalt. This interrupt will be generated whenever the hardware makes a new decision about the mitigation frequency. Change-Id: I408fb7e62ef13b21dfea68bb6b878cdbeee411cd Signed-off-by: Ram Chandrasekar --- arch/arm/boot/dts/qcom/msmcobalt.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 171a95afe5c6..b666f535a664 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -2698,10 +2698,12 @@ &clock_cpu { lmh_dcvs0: qcom,limits-dcvs@0 { compatible = "qcom,msm-hw-limits"; + interrupts = ; }; lmh_dcvs1: qcom,limits-dcvs@1 { compatible = "qcom,msm-hw-limits"; + interrupts = ; }; };