Merge changes I63d7ce3e,I6fda5ed9 into dev/msm-4.4-8996au

* changes:
  clk: msm: clock-cpu-8996: Allow interrupts during alt_pll set_rate
  clk: msm: clock-alpha-pll: Allow interrupts to be enabled during set_rate

drivers/clk/msm/clock-alpha-pll.c

@@ -612,13 +612,17 @@ static int alpha_pll_set_rate(struct clk *c, unsigned long rate)
 		return -EINVAL;
 	}
 
+	if (pll->no_irq_dis)
+		spin_lock(&c->lock);
+	else
+		spin_lock_irqsave(&c->lock, flags);
+
 	/*
 	 * For PLLs that do not support dynamic programming (dynamic_update
 	 * is not set), ensure PLL is off before changing rate. For
 	 * optimization reasons, assume no downstream clock is actively
 	 * using it.
 	 */
-	spin_lock_irqsave(&c->lock, flags);
 	if (c->count && !pll->dynamic_update)
 		c->ops->disable(c);
 
@@ -644,7 +648,10 @@ static int alpha_pll_set_rate(struct clk *c, unsigned long rate)
 	if (c->count && !pll->dynamic_update)
 		c->ops->enable(c);
 
-	spin_unlock_irqrestore(&c->lock, flags);
+	if (pll->no_irq_dis)
+		spin_unlock(&c->lock);
+	else
+		spin_unlock_irqrestore(&c->lock, flags);
 	return 0;
 }
 

drivers/clk/msm/clock-cpu-8996.c

@@ -238,6 +238,7 @@ static struct alpha_pll_clk perfcl_alt_pll = {
 	.post_div_config = 0x100, /* Div-2 */
 	.config_ctl_val = 0x4001051B,
 	.offline_bit_workaround = true,
+	.no_irq_dis = true,
 	.c = {
 		.always_on = true,
 		.parent = &alpha_xo_ao.c,
@@ -300,6 +301,7 @@ static struct alpha_pll_clk pwrcl_alt_pll = {
 	.post_div_config = 0x100, /* Div-2 */
 	.config_ctl_val = 0x4001051B,
 	.offline_bit_workaround = true,
+	.no_irq_dis = true,
 	.c = {
 		.always_on = true,
 		.dbg_name = "pwrcl_alt_pll",

include/soc/qcom/clock-alpha-pll.h

@@ -79,6 +79,7 @@ struct alpha_pll_clk {
 	 * that the workaround is required.
 	 */
 	bool offline_bit_workaround;
+	bool no_irq_dis;
 	bool is_fabia;
 	unsigned long min_supported_freq;
 	struct clk c;