ASoC: sdm660_cdc: fix HPH CnP on sdm660 internal codec
Enable digital clock bits before digital codec reset. Also update HD2 settings as per latest HW sequences. CRs-Fixed: 2018603 Change-Id: I270a324ffebc8b84ef23ff6b209efcde724f9b37 Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
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2 changed files with 5 additions and 5 deletions
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@ -1436,11 +1436,11 @@ static int msm_anlg_cdc_codec_enable_clock_block(struct snd_soc_codec *codec,
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if (enable) {
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snd_soc_update_bits(codec,
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MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30, 0x30);
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msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_CLK_ON);
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snd_soc_update_bits(codec,
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MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80, 0x80);
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snd_soc_update_bits(codec,
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MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x0C);
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msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_CLK_ON);
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} else {
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snd_soc_update_bits(codec,
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MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x00);
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@ -1028,7 +1028,7 @@ static int msm_dig_cdc_event_notify(struct notifier_block *block,
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break;
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case DIG_CDC_EVENT_PRE_RX1_INT_ON:
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snd_soc_update_bits(codec,
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MSM89XX_CDC_CORE_RX1_B3_CTL, 0x1C, 0x14);
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MSM89XX_CDC_CORE_RX1_B3_CTL, 0x3C, 0x28);
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snd_soc_update_bits(codec,
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MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0x10);
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snd_soc_update_bits(codec,
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@ -1036,7 +1036,7 @@ static int msm_dig_cdc_event_notify(struct notifier_block *block,
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break;
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case DIG_CDC_EVENT_PRE_RX2_INT_ON:
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snd_soc_update_bits(codec,
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MSM89XX_CDC_CORE_RX2_B3_CTL, 0x1C, 0x14);
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MSM89XX_CDC_CORE_RX2_B3_CTL, 0x3C, 0x28);
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snd_soc_update_bits(codec,
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MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0x10);
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snd_soc_update_bits(codec,
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@ -1044,7 +1044,7 @@ static int msm_dig_cdc_event_notify(struct notifier_block *block,
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break;
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case DIG_CDC_EVENT_POST_RX1_INT_OFF:
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snd_soc_update_bits(codec,
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MSM89XX_CDC_CORE_RX1_B3_CTL, 0x1C, 0x00);
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MSM89XX_CDC_CORE_RX1_B3_CTL, 0x3C, 0x00);
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snd_soc_update_bits(codec,
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MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0xFF);
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snd_soc_update_bits(codec,
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@ -1052,7 +1052,7 @@ static int msm_dig_cdc_event_notify(struct notifier_block *block,
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break;
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case DIG_CDC_EVENT_POST_RX2_INT_OFF:
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snd_soc_update_bits(codec,
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MSM89XX_CDC_CORE_RX2_B3_CTL, 0x1C, 0x00);
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MSM89XX_CDC_CORE_RX2_B3_CTL, 0x3C, 0x00);
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snd_soc_update_bits(codec,
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MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0xFF);
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snd_soc_update_bits(codec,
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