drm/nouveau/pm: some more delays for ddr3 reclocking
These numbers from the binary driver's daemon scripts, and fix the transition to perflvl 3 on my T510. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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9d6ba0b58c
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78c2018658
2 changed files with 4 additions and 0 deletions
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@ -978,6 +978,8 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
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break;
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break;
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case NV_MEM_TYPE_DDR3:
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case NV_MEM_TYPE_DDR3:
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tDLLK = 12000;
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tDLLK = 12000;
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tCKSRE = 2000;
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tXS = 1000;
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mr1_dlloff = 0x00000001;
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mr1_dlloff = 0x00000001;
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break;
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break;
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case NV_MEM_TYPE_GDDR3:
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case NV_MEM_TYPE_GDDR3:
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@ -1024,6 +1026,7 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
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exec->refresh_self(exec, false);
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exec->refresh_self(exec, false);
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exec->refresh_auto(exec, true);
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exec->refresh_auto(exec, true);
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exec->wait(exec, tXS);
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exec->wait(exec, tXS);
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exec->wait(exec, tXS);
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/* update MRs */
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/* update MRs */
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if (mr[2] != info->mr[2]) {
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if (mr[2] != info->mr[2]) {
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@ -344,6 +344,7 @@ mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
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static void
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static void
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mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
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mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
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{
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{
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volatile u32 post = nv_rd32(exec->dev, 0); (void)post;
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udelay((nsec + 500) / 1000);
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udelay((nsec + 500) / 1000);
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}
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}
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