From 78df37581d446d859c3d9c54fc7b51a3a9d9ac05 Mon Sep 17 00:00:00 2001
From: Sarangdhar Joshi <spjoshi@codeaurora.org>
Date: Tue, 8 Dec 2015 19:11:02 -0800
Subject: [PATCH] arm64: kernel: Update PERCPU_SECTION and RW_DATA_SECTION
 alignment

Update PERCPU_SECTION and RW_DATA_SECTION to align to L1_CACHE_BYTES
instead of hard coded 64 bytes since L1_CACHE_BYTES could get
updated to more than 64 bytes cacheline size.

Change-Id: I0bc1f0420675cf65e958c53a230357918f05aabc
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
---
 arch/arm64/kernel/vmlinux.lds.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 71426a78db12..b3f48316f888 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -11,6 +11,7 @@
 #include <asm/memory.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
+#include <asm/cache.h>
 
 #include "image.h"