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mmc: sdhci-msm: Improvise tuning to check the card status

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Right now only certain amount of delay (146 MCLK cycles as per spec)
is given for card to return back to transfer state upon any CMD error
that host controller may receive. This delay seems to be insufficient
for certain eMMC cards like Hynix. This patch tries to send CMD13 and
also retry it with the same delay to make sure the card is back to
transfer state before sending next command. Otherwise we may see auto
cmd or illegal command failures to the read command sent right after
tuning, especially if the last tuning phase has failed.

Change-Id: I3ec2da150dc5ee656b8156040bf539812b0e4d2b
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This commit is contained in:
Sahitya Tummala 2015-02-25 14:24:52 +05:30 • committed by Subhash Jadavani
parent 2cfffa3bbe
commit 7a14825b8e
1 changed files with 31 additions and 8 deletions
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39
drivers/mmc/host/sdhci-msm.c
View file

@ -932,6 +932,7 @@ int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
u8 drv_type = 0;
bool drv_type_changed = false;
struct mmc_card *card = host->mmc->card;
int sts_retry;
/*
* Tuning is required for SDR104, HS200 and HS400 cards and
@ -988,6 +989,7 @@ retry:
.data = &data
};
struct scatterlist sg;
struct mmc_command sts_cmd = {0};
/* set the phase in delay line hw block */
rc = msm_config_cm_dll_phase(host, phase);
@ -1008,14 +1010,35 @@ retry:
memset(data_buf, 0, size);
mmc_wait_for_req(mmc, &mrq);
/*
* wait for 146 MCLK cycles for the card to send out the data
* and thus move to TRANS state. As the MCLK would be minimum
* 200MHz when tuning is performed, we need maximum 0.73us
* delay. To be on safer side 1ms delay is given.
*/
if (cmd.error)
usleep_range(1000, 1200);
if (card && (cmd.error || data.error)) {
sts_cmd.opcode = MMC_SEND_STATUS;
sts_cmd.arg = card->rca << 16;
sts_cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
sts_retry = 5;
while (sts_retry) {
mmc_wait_for_cmd(mmc, &sts_cmd, 0);
if (sts_cmd.error ||
(R1_CURRENT_STATE(sts_cmd.resp[0])
!= R1_STATE_TRAN)) {
sts_retry--;
/*
* wait for at least 146 MCLK cycles for
* the card to move to TRANS state. As
* the MCLK would be min 200MHz for
* tuning, we need max 0.73us delay. To
* be on safer side 1ms delay is given.
*/
usleep_range(1000, 1200);
pr_debug("%s: phase %d sts cmd err %d resp 0x%x\n",
mmc_hostname(mmc), phase,
sts_cmd.error, sts_cmd.resp[0]);
continue;
}
break;
};
}
if (!cmd.error && !data.error &&
!memcmp(data_buf, tuning_block_pattern, size)) {
/* tuning is successful at this tuning point */