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arm: at91: dt: at91sam9 add nand pinctrl support

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Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD 2012-07-12 23:36:52 +08:00
parent 0cdc7e8e11
commit 7a38d450b6
5 changed files with 50 additions and 0 deletions
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10
arch/arm/boot/dts/at91sam9260.dtsi
View file

@ -208,6 +208,14 @@
}; };
}; };
nand {
pinctrl_nand: nand-0 {
atmel,pins =
<2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
};
};
pioA: gpio@fffff400 { pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio"; compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>; reg = <0xfffff400 0x200>;
@ -382,6 +390,8 @@
>; >;
atmel,nand-addr-offset = <21>; atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>; atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
gpios = <&pioC 13 0 gpios = <&pioC 13 0
&pioC 14 0 &pioC 14 0
0 0

10
arch/arm/boot/dts/at91sam9263.dtsi
View file

@ -155,6 +155,14 @@
}; };
}; };
nand {
pinctrl_nand: nand-0 {
atmel,pins =
<0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
};
};
pioA: gpio@fffff200 { pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio"; compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>; reg = <0xfffff200 0x200>;
@ -281,6 +289,8 @@
>; >;
atmel,nand-addr-offset = <21>; atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>; atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
gpios = <&pioA 22 0 gpios = <&pioA 22 0
&pioD 15 0 &pioD 15 0
0 0

10
arch/arm/boot/dts/at91sam9g45.dtsi
View file

@ -188,6 +188,14 @@
}; };
}; };
nand {
pinctrl_nand: nand-0 {
atmel,pins =
<2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
};
};
pioA: gpio@fffff200 { pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio"; compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>; reg = <0xfffff200 0x200>;
@ -364,6 +372,8 @@
>; >;
atmel,nand-addr-offset = <21>; atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>; atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
gpios = <&pioC 8 0 gpios = <&pioC 8 0
&pioC 14 0 &pioC 14 0
0 0

10
arch/arm/boot/dts/at91sam9n12.dtsi
View file

@ -191,6 +191,14 @@
}; };
}; };
nand {
pinctrl_nand: nand-0 {
atmel,pins =
<3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
};
};
pioA: gpio@fffff400 { pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>; reg = <0xfffff400 0x200>;
@ -315,6 +323,8 @@
>; >;
atmel,nand-addr-offset = <21>; atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>; atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
gpios = <&pioD 5 0 gpios = <&pioD 5 0
&pioD 4 0 &pioD 4 0
0 0

10
arch/arm/boot/dts/at91sam9x5.dtsi
View file

@ -198,6 +198,14 @@
}; };
}; };
nand {
pinctrl_nand: nand-0 {
atmel,pins =
<3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
};
};
pioA: gpio@fffff400 { pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>; reg = <0xfffff400 0x200>;
@ -371,6 +379,8 @@
>; >;
atmel,nand-addr-offset = <21>; atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>; atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
gpios = <&pioD 5 0 gpios = <&pioD 5 0
&pioD 4 0 &pioD 4 0
0 0