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msm: ep_pcie: support multiple link training options

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Add the support to trigger link training based on PCIe PHY version.

Change-Id: I4c765797d8e8adf5c15effae95da350a0d8ec0c3
Signed-off-by: Yan He <yanhe@codeaurora.org>
This commit is contained in:
Yan He 2015-05-29 18:13:21 -07:00 • committed by David Keitel
parent 1e5604cf01
commit 7adcccb4d1
2 changed files with 5 additions and 1 deletions
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1
drivers/platform/msm/ep_pcie/ep_pcie_com.h
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@ -42,6 +42,7 @@
#define PCIE20_PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1A4
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x1A8
#define PCIE20_PARF_Q2A_FLUSH 0x1AC
#define PCIE20_PARF_LTSSM 0x1B0
#define PCIE20_PARF_DEVICE_TYPE 0x1000
#define PCIE20_ELBI_VERSION 0x00

5
drivers/platform/msm/ep_pcie/ep_pcie_core.c
View file

@ -1061,7 +1061,10 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
ep_pcie_config_inbound_iatu(dev);
/* enable link training */
ep_pcie_write_mask(dev->elbi + PCIE20_ELBI_SYS_CTRL, 0, BIT(0));
if (dev->phy_rev >= 3)
ep_pcie_write_mask(dev->parf + PCIE20_PARF_LTSSM, 0, BIT(8));
else
ep_pcie_write_mask(dev->elbi + PCIE20_ELBI_SYS_CTRL, 0, BIT(0));
EP_PCIE_DBG(dev, "PCIe V%d: check if link is up\n", dev->rev);