arm64: cache: change ARCH_DMA_MINALIGN and L1_CACHE_SHIFT values

This reverts 'commit 9730348075 ("arm64: Increase the max
granular size") and also sets ARM_DMA_MINALIGN to 128.
ARCH_DMA_MINALIGN is dependent on L1_CACHE_SHIFT but it should
be set to maximum *known* cache line size on ARMv8 systems to
avoid DMA coherecy issues. So setting ARM_DMA_MINALIGN to 128.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Change-Id: Ie771d1b693789fce8793538a6efddfe68e2a0043
Patch-mainline: linux-kernel @ 21/03/16, 17:14:03
Signed-off-by: Imran Khan <kimran@codeaurora.org>
This commit is contained in:
Imran Khan 2017-04-03 13:11:18 +05:30 committed by Gerrit - the friendly Code Review server
parent 7f0d77b390
commit 7b9683892c
2 changed files with 9 additions and 9 deletions

View file

@ -18,17 +18,17 @@
#include <asm/cachetype.h>
#define L1_CACHE_SHIFT 7
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/*
* Memory returned by kmalloc() may be used for DMA, so we must make
* sure that all such allocations are cache aligned. Otherwise,
* unrelated code may cause parts of the buffer to be read into the
* cache before the transfer is done, causing old data to be seen by
* the CPU.
* sure that all such allocations are aligned to the maximum *known*
* cache line size on ARMv8 systems. Otherwise, unrelated code may
* cause parts of the buffer to be read into the cache before the
* transfer is done, causing old data to be seen by the CPU.
*/
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
#define ARCH_DMA_MINALIGN (128)
#ifndef __ASSEMBLY__

View file

@ -992,9 +992,9 @@ void __init setup_cpu_features(void)
if (!cwg)
pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
cls);
if (L1_CACHE_BYTES < cls)
pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
L1_CACHE_BYTES, cls);
if (ARCH_DMA_MINALIGN < cls)
pr_warn("ARCH_DMA_MINALIGN smaller than the Cache Writeback Granule (%d < %d)\n",
ARCH_DMA_MINALIGN, cls);
}
static bool __maybe_unused