From 7c8c5976a7ec4c467e348c25b25adba600437faa Mon Sep 17 00:00:00 2001 From: Carl Vanderlip Date: Fri, 25 Oct 2013 12:04:26 -0700 Subject: [PATCH] msm: mdss: Balance clock requests in histogram enable Balance the clock requests in histogram enable to prevent clocks from being left on. Change-Id: I45fc029049b68cceb56d0dc40f7819aca0625a58 Signed-off-by: Carl Vanderlip --- drivers/video/fbdev/msm/mdss_mdp_pp.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/video/fbdev/msm/mdss_mdp_pp.c b/drivers/video/fbdev/msm/mdss_mdp_pp.c index 94379806ced0..000ff4263e04 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_pp.c +++ b/drivers/video/fbdev/msm/mdss_mdp_pp.c @@ -2771,7 +2771,7 @@ int mdss_mdp_histogram_start(struct mdp_histogram_start_req *req) if (!i) { ret = -EINVAL; pr_warn("Must pass pipe arguments, %d", i); - goto hist_exit; + goto hist_stop_clk; } for (i = 0; i < MDSS_PP_ARG_NUM; i++) { @@ -2781,10 +2781,9 @@ int mdss_mdp_histogram_start(struct mdp_histogram_start_req *req) if (IS_ERR_OR_NULL(pipe)) continue; if (!pipe || pipe->num > MDSS_MDP_SSPP_VIG2) { - mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false); ret = -EINVAL; pr_warn("Invalid Hist pipe (%d)", i); - goto hist_exit; + goto hist_stop_clk; } done_shift_bit = (pipe->num * 4); hist_info = &pipe->pp_res.hist; @@ -2807,8 +2806,8 @@ int mdss_mdp_histogram_start(struct mdp_histogram_start_req *req) PP_FLAGS_DIRTY_HIST_COL; } } +hist_stop_clk: mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false); - hist_exit: return ret; }