Merge "qpnp-fg-gen3: fix ESR filter configuration"
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7d1b06177e
1 changed files with 137 additions and 101 deletions
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@ -167,11 +167,11 @@ static struct fg_sram_param pmi8998_v1_sram_params[] = {
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fg_decode_default),
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PARAM(FULL_SOC, FULL_SOC_WORD, FULL_SOC_OFFSET, 2, 1, 1, 0, NULL,
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fg_decode_default),
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PARAM(VOLTAGE_PRED, VOLTAGE_PRED_WORD, VOLTAGE_PRED_OFFSET, 2, 244141,
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1000, 0, NULL, fg_decode_voltage_15b),
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PARAM(OCV, OCV_WORD, OCV_OFFSET, 2, 244141, 1000, 0, NULL,
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PARAM(VOLTAGE_PRED, VOLTAGE_PRED_WORD, VOLTAGE_PRED_OFFSET, 2, 1000,
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244141, 0, NULL, fg_decode_voltage_15b),
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PARAM(OCV, OCV_WORD, OCV_OFFSET, 2, 1000, 244141, 0, NULL,
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fg_decode_voltage_15b),
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PARAM(RSLOW, RSLOW_WORD, RSLOW_OFFSET, 2, 244141, 1000, 0, NULL,
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PARAM(RSLOW, RSLOW_WORD, RSLOW_OFFSET, 2, 1000, 244141, 0, NULL,
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fg_decode_value_16b),
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PARAM(ALG_FLAGS, ALG_FLAGS_WORD, ALG_FLAGS_OFFSET, 1, 1, 1, 0, NULL,
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fg_decode_default),
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@ -188,8 +188,8 @@ static struct fg_sram_param pmi8998_v1_sram_params[] = {
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-2500, fg_encode_voltage, NULL),
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PARAM(VBATT_LOW, VBATT_LOW_WORD, VBATT_LOW_OFFSET, 1, 100000, 390625,
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-2500, fg_encode_voltage, NULL),
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PARAM(VBATT_FULL, VBATT_FULL_WORD, VBATT_FULL_OFFSET, 2, 1000000,
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244141, 0, fg_encode_voltage, NULL),
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PARAM(VBATT_FULL, VBATT_FULL_WORD, VBATT_FULL_OFFSET, 2, 1000,
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244141, 0, fg_encode_voltage, fg_decode_voltage_15b),
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PARAM(SYS_TERM_CURR, SYS_TERM_CURR_WORD, SYS_TERM_CURR_OFFSET, 3,
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1000000, 122070, 0, fg_encode_current, NULL),
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PARAM(CHG_TERM_CURR, CHG_TERM_CURR_WORD, CHG_TERM_CURR_OFFSET, 1,
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@ -227,11 +227,11 @@ static struct fg_sram_param pmi8998_v2_sram_params[] = {
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fg_decode_default),
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PARAM(FULL_SOC, FULL_SOC_WORD, FULL_SOC_OFFSET, 2, 1, 1, 0, NULL,
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fg_decode_default),
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PARAM(VOLTAGE_PRED, VOLTAGE_PRED_WORD, VOLTAGE_PRED_OFFSET, 2, 244141,
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1000, 0, NULL, fg_decode_voltage_15b),
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PARAM(OCV, OCV_WORD, OCV_OFFSET, 2, 244141, 1000, 0, NULL,
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PARAM(VOLTAGE_PRED, VOLTAGE_PRED_WORD, VOLTAGE_PRED_OFFSET, 2, 1000,
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244141, 0, NULL, fg_decode_voltage_15b),
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PARAM(OCV, OCV_WORD, OCV_OFFSET, 2, 1000, 244141, 0, NULL,
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fg_decode_voltage_15b),
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PARAM(RSLOW, RSLOW_WORD, RSLOW_OFFSET, 2, 244141, 1000, 0, NULL,
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PARAM(RSLOW, RSLOW_WORD, RSLOW_OFFSET, 2, 1000, 244141, 0, NULL,
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fg_decode_value_16b),
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PARAM(ALG_FLAGS, ALG_FLAGS_WORD, ALG_FLAGS_OFFSET, 1, 1, 1, 0, NULL,
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fg_decode_default),
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@ -250,8 +250,8 @@ static struct fg_sram_param pmi8998_v2_sram_params[] = {
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15625, -2000, fg_encode_voltage, NULL),
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PARAM(FLOAT_VOLT, FLOAT_VOLT_v2_WORD, FLOAT_VOLT_v2_OFFSET, 1, 1000,
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15625, -2000, fg_encode_voltage, NULL),
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PARAM(VBATT_FULL, VBATT_FULL_WORD, VBATT_FULL_OFFSET, 2, 1000000,
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244141, 0, fg_encode_voltage, NULL),
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PARAM(VBATT_FULL, VBATT_FULL_WORD, VBATT_FULL_OFFSET, 2, 1000,
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244141, 0, fg_encode_voltage, fg_decode_voltage_15b),
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PARAM(SYS_TERM_CURR, SYS_TERM_CURR_WORD, SYS_TERM_CURR_OFFSET, 3,
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1000000, 122070, 0, fg_encode_current, NULL),
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PARAM(CHG_TERM_CURR, CHG_TERM_CURR_v2_WORD, CHG_TERM_CURR_v2_OFFSET, 1,
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@ -374,7 +374,7 @@ static int fg_decode_voltage_15b(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int value)
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{
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value &= VOLTAGE_15BIT_MASK;
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sp[id].value = div_u64((u64)value * sp[id].numrtr, sp[id].denmtr);
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sp[id].value = div_u64((u64)value * sp[id].denmtr, sp[id].numrtr);
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pr_debug("id: %d raw value: %x decoded value: %x\n", id, value,
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sp[id].value);
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return sp[id].value;
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@ -383,7 +383,7 @@ static int fg_decode_voltage_15b(struct fg_sram_param *sp,
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static int fg_decode_cc_soc(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int value)
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{
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sp[id].value = div_s64((s64)value * sp[id].numrtr, sp[id].denmtr);
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sp[id].value = div_s64((s64)value * sp[id].denmtr, sp[id].numrtr);
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sp[id].value = sign_extend32(sp[id].value, 31);
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pr_debug("id: %d raw value: %x decoded value: %x\n", id, value,
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sp[id].value);
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@ -393,7 +393,7 @@ static int fg_decode_cc_soc(struct fg_sram_param *sp,
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static int fg_decode_value_16b(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int value)
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{
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sp[id].value = div_u64((u64)(u16)value * sp[id].numrtr, sp[id].denmtr);
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sp[id].value = div_u64((u64)(u16)value * sp[id].denmtr, sp[id].numrtr);
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pr_debug("id: %d raw value: %x decoded value: %x\n", id, value,
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sp[id].value);
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return sp[id].value;
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@ -855,23 +855,50 @@ static const char *fg_get_battery_type(struct fg_chip *chip)
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return DEFAULT_BATT_TYPE;
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}
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static int fg_get_batt_id(struct fg_chip *chip, int *val)
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static int fg_batt_missing_config(struct fg_chip *chip, bool enable)
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{
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int rc, batt_id = -EINVAL;
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int rc;
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rc = fg_masked_write(chip, BATT_INFO_BATT_MISS_CFG(chip),
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BM_FROM_BATT_ID_BIT, enable ? BM_FROM_BATT_ID_BIT : 0);
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if (rc < 0)
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pr_err("Error in writing to %04x, rc=%d\n",
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BATT_INFO_BATT_MISS_CFG(chip), rc);
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return rc;
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}
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static int fg_get_batt_id(struct fg_chip *chip)
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{
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int rc, ret, batt_id = 0;
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if (!chip->batt_id_chan)
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return -EINVAL;
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rc = iio_read_channel_processed(chip->batt_id_chan, &batt_id);
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rc = fg_batt_missing_config(chip, false);
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if (rc < 0) {
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pr_err("Error in reading batt_id channel, rc:%d\n", rc);
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pr_err("Error in disabling BMD, rc=%d\n", rc);
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return rc;
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}
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fg_dbg(chip, FG_STATUS, "batt_id: %d\n", batt_id);
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rc = iio_read_channel_processed(chip->batt_id_chan, &batt_id);
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if (rc < 0) {
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pr_err("Error in reading batt_id channel, rc:%d\n", rc);
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goto out;
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}
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*val = batt_id;
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return 0;
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/* Wait for 200ms before enabling BMD again */
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msleep(200);
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fg_dbg(chip, FG_STATUS, "batt_id: %d\n", batt_id);
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chip->batt_id_ohms = batt_id;
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out:
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ret = fg_batt_missing_config(chip, true);
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if (ret < 0) {
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pr_err("Error in enabling BMD, ret=%d\n", ret);
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return ret;
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}
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return rc;
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}
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static int fg_get_batt_profile(struct fg_chip *chip)
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@ -879,24 +906,16 @@ static int fg_get_batt_profile(struct fg_chip *chip)
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struct device_node *node = chip->dev->of_node;
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struct device_node *batt_node, *profile_node;
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const char *data;
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int rc, len, batt_id;
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int rc, len;
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rc = fg_get_batt_id(chip, &batt_id);
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if (rc < 0) {
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pr_err("Error in getting batt_id rc:%d\n", rc);
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return rc;
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}
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chip->batt_id_ohms = batt_id;
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batt_id /= 1000;
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batt_node = of_find_node_by_name(node, "qcom,battery-data");
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if (!batt_node) {
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pr_err("Batterydata not available\n");
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return -ENXIO;
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}
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profile_node = of_batterydata_get_best_profile(batt_node, batt_id,
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NULL);
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profile_node = of_batterydata_get_best_profile(batt_node,
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chip->batt_id_ohms / 1000, NULL);
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if (IS_ERR(profile_node))
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return PTR_ERR(profile_node);
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@ -946,6 +965,7 @@ static int fg_get_batt_profile(struct fg_chip *chip)
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chip->profile_available = true;
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memcpy(chip->batt_profile, data, len);
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return 0;
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}
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@ -1660,6 +1680,29 @@ static int fg_rconn_config(struct fg_chip *chip)
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return 0;
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}
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static int fg_set_constant_chg_voltage(struct fg_chip *chip, int volt_uv)
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{
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u8 buf[2];
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int rc;
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if (volt_uv <= 0 || volt_uv > 15590000) {
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pr_err("Invalid voltage %d\n", volt_uv);
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return -EINVAL;
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}
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fg_encode(chip->sp, FG_SRAM_VBATT_FULL, volt_uv, buf);
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_VBATT_FULL].addr_word,
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chip->sp[FG_SRAM_VBATT_FULL].addr_byte, buf,
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chip->sp[FG_SRAM_VBATT_FULL].len, FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error in writing vbatt_full, rc=%d\n", rc);
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return rc;
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}
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return 0;
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}
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static int fg_set_recharge_soc(struct fg_chip *chip, int recharge_soc)
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{
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u8 buf;
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@ -1742,39 +1785,41 @@ static int fg_esr_filter_config(struct fg_chip *chip, int batt_temp)
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/*
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* If battery temperature is lesser than 10 C (default), then apply the
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* normal ESR tight and broad filter values to ESR low temperature tight
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* and broad filters. If battery temperature is higher than 10 C, then
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* apply back the low temperature ESR filter coefficients to ESR low
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* temperature tight and broad filters.
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* ESR low temperature tight and broad filter values to ESR room
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* temperature tight and broad filters. If battery temperature is higher
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* than 10 C, then apply back the room temperature ESR filter
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* coefficients to ESR room temperature tight and broad filters.
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*/
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if (batt_temp > chip->dt.esr_flt_switch_temp
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&& chip->esr_flt_cold_temp_en) {
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fg_encode(chip->sp, FG_SRAM_ESR_TIGHT_FILTER,
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chip->dt.esr_tight_lt_flt_upct, &esr_tight_lt_flt);
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fg_encode(chip->sp, FG_SRAM_ESR_BROAD_FILTER,
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chip->dt.esr_broad_lt_flt_upct, &esr_broad_lt_flt);
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} else if (batt_temp <= chip->dt.esr_flt_switch_temp
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&& !chip->esr_flt_cold_temp_en) {
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fg_encode(chip->sp, FG_SRAM_ESR_TIGHT_FILTER,
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chip->dt.esr_tight_flt_upct, &esr_tight_lt_flt);
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fg_encode(chip->sp, FG_SRAM_ESR_BROAD_FILTER,
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chip->dt.esr_broad_flt_upct, &esr_broad_lt_flt);
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} else if (batt_temp <= chip->dt.esr_flt_switch_temp
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&& !chip->esr_flt_cold_temp_en) {
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fg_encode(chip->sp, FG_SRAM_ESR_TIGHT_FILTER,
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chip->dt.esr_tight_lt_flt_upct, &esr_tight_lt_flt);
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fg_encode(chip->sp, FG_SRAM_ESR_BROAD_FILTER,
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chip->dt.esr_broad_lt_flt_upct, &esr_broad_lt_flt);
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cold_temp = true;
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} else {
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return 0;
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}
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rc = fg_sram_write(chip, ESR_FILTER_WORD,
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ESR_UPD_TIGHT_LOW_TEMP_OFFSET, &esr_tight_lt_flt, 1,
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FG_IMA_DEFAULT);
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_ESR_TIGHT_FILTER].addr_word,
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chip->sp[FG_SRAM_ESR_TIGHT_FILTER].addr_byte,
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&esr_tight_lt_flt,
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chip->sp[FG_SRAM_ESR_TIGHT_FILTER].len, FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error in writing ESR LT tight filter, rc=%d\n", rc);
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return rc;
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}
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rc = fg_sram_write(chip, ESR_FILTER_WORD,
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ESR_UPD_BROAD_LOW_TEMP_OFFSET, &esr_broad_lt_flt, 1,
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FG_IMA_DEFAULT);
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_ESR_BROAD_FILTER].addr_word,
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chip->sp[FG_SRAM_ESR_BROAD_FILTER].addr_byte,
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&esr_broad_lt_flt,
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chip->sp[FG_SRAM_ESR_BROAD_FILTER].len, FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error in writing ESR LT broad filter, rc=%d\n", rc);
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return rc;
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@ -1853,18 +1898,6 @@ static int fg_esr_fcc_config(struct fg_chip *chip)
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return 0;
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}
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static int fg_batt_missing_config(struct fg_chip *chip, bool enable)
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{
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int rc;
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rc = fg_masked_write(chip, BATT_INFO_BATT_MISS_CFG(chip),
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BM_FROM_BATT_ID_BIT, enable ? BM_FROM_BATT_ID_BIT : 0);
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if (rc < 0)
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pr_err("Error in writing to %04x, rc=%d\n",
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BATT_INFO_BATT_MISS_CFG(chip), rc);
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return rc;
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}
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static void fg_batt_avg_update(struct fg_chip *chip)
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{
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if (chip->charge_status == chip->prev_charge_status)
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@ -2725,6 +2758,9 @@ static int fg_psy_get_property(struct power_supply *psy,
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case POWER_SUPPLY_PROP_DEBUG_BATTERY:
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pval->intval = is_debug_batt_id(chip);
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break;
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case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
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rc = fg_get_sram_prop(chip, FG_SRAM_VBATT_FULL, &pval->intval);
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break;
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default:
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pr_err("unsupported property %d\n", psp);
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rc = -EINVAL;
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@ -2742,6 +2778,7 @@ static int fg_psy_set_property(struct power_supply *psy,
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const union power_supply_propval *pval)
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{
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struct fg_chip *chip = power_supply_get_drvdata(psy);
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int rc = 0;
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switch (psp) {
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case POWER_SUPPLY_PROP_CYCLE_COUNT_ID:
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@ -2752,12 +2789,14 @@ static int fg_psy_set_property(struct power_supply *psy,
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pval->intval);
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return -EINVAL;
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}
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case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
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rc = fg_set_constant_chg_voltage(chip, pval->intval);
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break;
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default:
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break;
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}
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return 0;
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return rc;
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}
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static int fg_property_is_writeable(struct power_supply *psy,
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@ -2765,6 +2804,7 @@ static int fg_property_is_writeable(struct power_supply *psy,
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{
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switch (psp) {
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case POWER_SUPPLY_PROP_CYCLE_COUNT_ID:
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case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
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return 1;
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default:
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break;
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@ -2824,6 +2864,7 @@ static enum power_supply_property fg_psy_props[] = {
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POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG,
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POWER_SUPPLY_PROP_SOC_REPORTING_READY,
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POWER_SUPPLY_PROP_DEBUG_BATTERY,
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POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE,
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};
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static const struct power_supply_desc fg_psy_desc = {
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@ -2877,16 +2918,11 @@ static int fg_hw_init(struct fg_chip *chip)
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}
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if (chip->bp.vbatt_full_mv > 0) {
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fg_encode(chip->sp, FG_SRAM_VBATT_FULL, chip->bp.vbatt_full_mv,
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buf);
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_VBATT_FULL].addr_word,
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chip->sp[FG_SRAM_VBATT_FULL].addr_byte, buf,
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chip->sp[FG_SRAM_VBATT_FULL].len, FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error in writing vbatt_full, rc=%d\n", rc);
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rc = fg_set_constant_chg_voltage(chip,
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chip->bp.vbatt_full_mv * 1000);
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if (rc < 0)
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return rc;
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}
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}
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fg_encode(chip->sp, FG_SRAM_CHG_TERM_CURR, chip->dt.chg_term_curr_ma,
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buf);
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@ -3142,9 +3178,10 @@ static irqreturn_t fg_batt_missing_irq_handler(int irq, void *data)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
rc = fg_batt_missing_config(chip, false);
|
||||
rc = fg_get_batt_id(chip);
|
||||
if (rc < 0) {
|
||||
pr_err("Error in disabling BMD, rc=%d\n", rc);
|
||||
chip->soc_reporting_ready = true;
|
||||
pr_err("Error in getting battery id, rc:%d\n", rc);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
|
@ -3152,19 +3189,12 @@ static irqreturn_t fg_batt_missing_irq_handler(int irq, void *data)
|
|||
if (rc < 0) {
|
||||
chip->soc_reporting_ready = true;
|
||||
pr_err("Error in getting battery profile, rc:%d\n", rc);
|
||||
goto enable_bmd;
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
clear_battery_profile(chip);
|
||||
schedule_delayed_work(&chip->profile_load_work, 0);
|
||||
|
||||
enable_bmd:
|
||||
/* Wait for 200ms before enabling BMD again */
|
||||
msleep(200);
|
||||
rc = fg_batt_missing_config(chip, true);
|
||||
if (rc < 0)
|
||||
pr_err("Error in enabling BMD, rc=%d\n", rc);
|
||||
|
||||
if (chip->fg_psy)
|
||||
power_supply_changed(chip->fg_psy);
|
||||
|
||||
|
|
@ -3571,16 +3601,6 @@ static int fg_parse_dt(struct fg_chip *chip)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
chip->batt_id_chan = iio_channel_get(chip->dev, "rradc_batt_id");
|
||||
if (IS_ERR(chip->batt_id_chan)) {
|
||||
if (PTR_ERR(chip->batt_id_chan) != -EPROBE_DEFER)
|
||||
pr_err("batt_id_chan unavailable %ld\n",
|
||||
PTR_ERR(chip->batt_id_chan));
|
||||
rc = PTR_ERR(chip->batt_id_chan);
|
||||
chip->batt_id_chan = NULL;
|
||||
return rc;
|
||||
}
|
||||
|
||||
if (of_get_available_child_count(node) == 0) {
|
||||
dev_err(chip->dev, "No child nodes specified!\n");
|
||||
return -ENXIO;
|
||||
|
|
@ -3625,13 +3645,6 @@ static int fg_parse_dt(struct fg_chip *chip)
|
|||
}
|
||||
chip->rradc_base = base;
|
||||
|
||||
rc = fg_get_batt_profile(chip);
|
||||
if (rc < 0) {
|
||||
chip->soc_reporting_ready = true;
|
||||
pr_warn("profile for batt_id=%dKOhms not found..using OTP, rc:%d\n",
|
||||
chip->batt_id_ohms / 1000, rc);
|
||||
}
|
||||
|
||||
/* Read all the optional properties below */
|
||||
rc = of_property_read_u32(node, "qcom,fg-cutoff-voltage", &temp);
|
||||
if (rc < 0)
|
||||
|
|
@ -3867,10 +3880,13 @@ static int fg_gen3_probe(struct platform_device *pdev)
|
|||
return -ENXIO;
|
||||
}
|
||||
|
||||
rc = fg_parse_dt(chip);
|
||||
if (rc < 0) {
|
||||
dev_err(chip->dev, "Error in reading DT parameters, rc:%d\n",
|
||||
rc);
|
||||
chip->batt_id_chan = iio_channel_get(chip->dev, "rradc_batt_id");
|
||||
if (IS_ERR(chip->batt_id_chan)) {
|
||||
if (PTR_ERR(chip->batt_id_chan) != -EPROBE_DEFER)
|
||||
pr_err("batt_id_chan unavailable %ld\n",
|
||||
PTR_ERR(chip->batt_id_chan));
|
||||
rc = PTR_ERR(chip->batt_id_chan);
|
||||
chip->batt_id_chan = NULL;
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
|
@ -3881,6 +3897,13 @@ static int fg_gen3_probe(struct platform_device *pdev)
|
|||
return rc;
|
||||
}
|
||||
|
||||
rc = fg_parse_dt(chip);
|
||||
if (rc < 0) {
|
||||
dev_err(chip->dev, "Error in reading DT parameters, rc:%d\n",
|
||||
rc);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
mutex_init(&chip->bus_lock);
|
||||
mutex_init(&chip->sram_rw_lock);
|
||||
mutex_init(&chip->cyc_ctr.lock);
|
||||
|
|
@ -3895,6 +3918,19 @@ static int fg_gen3_probe(struct platform_device *pdev)
|
|||
INIT_DELAYED_WORK(&chip->batt_avg_work, batt_avg_work);
|
||||
INIT_DELAYED_WORK(&chip->sram_dump_work, sram_dump_work);
|
||||
|
||||
rc = fg_get_batt_id(chip);
|
||||
if (rc < 0) {
|
||||
pr_err("Error in getting battery id, rc:%d\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
rc = fg_get_batt_profile(chip);
|
||||
if (rc < 0) {
|
||||
chip->soc_reporting_ready = true;
|
||||
pr_warn("profile for batt_id=%dKOhms not found..using OTP, rc:%d\n",
|
||||
chip->batt_id_ohms / 1000, rc);
|
||||
}
|
||||
|
||||
rc = fg_memif_init(chip);
|
||||
if (rc < 0) {
|
||||
dev_err(chip->dev, "Error in initializing FG_MEMIF, rc:%d\n",
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue