Revert "FROMLIST: arm64: Disable TTBR0_EL1 during normal kernel execution"
This reverts commit 5775ca3482.
Bug: 31432001
Change-Id: I9b07c2f01bc2bcfed51f60ab487034639f5e1960
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
This commit is contained in:
Sami Tolvanen
Amit Pundir
parent
23640f2207
commit
7e73e2156c
6 changed files with 16 additions and 146 deletions
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@ -1,7 +1,6 @@
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#ifndef _ASM_EFI_H
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#define _ASM_EFI_H
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#include <asm/cpufeature.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <asm/neon.h>
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@ -70,30 +69,7 @@ int efi_create_mapping(struct mm_struct *mm, efi_memory_desc_t *md);
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static inline void efi_set_pgd(struct mm_struct *mm)
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{
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__switch_mm(mm);
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if (system_uses_ttbr0_pan()) {
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if (mm != current->active_mm) {
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/*
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* Update the current thread's saved ttbr0 since it is
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* restored as part of a return from exception. Set
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* the hardware TTBR0_EL1 using cpu_switch_mm()
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* directly to enable potential errata workarounds.
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*/
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update_saved_ttbr0(current, mm);
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cpu_switch_mm(mm->pgd, mm);
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} else {
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/*
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* Defer the switch to the current thread's TTBR0_EL1
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* until uaccess_enable(). Restore the current
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* thread's saved ttbr0 corresponding to its active_mm
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* (if different from init_mm).
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*/
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cpu_set_reserved_ttbr0();
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if (current->active_mm != &init_mm)
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update_saved_ttbr0(current, current->active_mm);
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}
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}
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switch_mm(NULL, mm, NULL);
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}
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void efi_virtmap_load(void);
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@ -23,7 +23,6 @@
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#include <linux/sched.h>
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#include <asm/cacheflush.h>
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#include <asm/cpufeature.h>
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#include <asm/proc-fns.h>
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#include <asm-generic/mm_hooks.h>
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#include <asm/cputype.h>
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@ -114,7 +113,7 @@ static inline void cpu_uninstall_idmap(void)
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local_flush_tlb_all();
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cpu_set_default_tcr_t0sz();
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if (mm != &init_mm && !system_uses_ttbr0_pan())
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if (mm != &init_mm)
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cpu_switch_mm(mm->pgd, mm);
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}
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@ -174,27 +173,21 @@ enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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static inline void update_saved_ttbr0(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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if (system_uses_ttbr0_pan()) {
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BUG_ON(mm->pgd == swapper_pg_dir);
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task_thread_info(tsk)->ttbr0 =
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virt_to_phys(mm->pgd) | ASID(mm) << 48;
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}
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}
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#else
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static inline void update_saved_ttbr0(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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}
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#endif
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static inline void __switch_mm(struct mm_struct *next)
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/*
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* This is the actual mm switch as far as the scheduler
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* is concerned. No registers are touched. We avoid
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* calling the CPU specific function when the mm hasn't
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* actually changed.
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*/
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static inline void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned int cpu = smp_processor_id();
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if (prev == next)
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return;
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/*
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* init_mm.pgd does not contain any user mappings and it is always
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* active for kernel addresses in TTBR1. Just set the reserved TTBR0.
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@ -207,23 +200,7 @@ static inline void __switch_mm(struct mm_struct *next)
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check_and_switch_context(next, cpu);
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}
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static inline void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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if (prev != next)
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__switch_mm(next);
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/*
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* Update the saved TTBR0_EL1 of the scheduled-in task as the previous
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* value may have not been initialised yet (activate_mm caller) or the
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* ASID has changed since the last run (following the context switch
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* of another thread of the same process).
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*/
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update_saved_ttbr0(tsk, next);
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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#define activate_mm(prev,next) switch_mm(prev, next, current)
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#define activate_mm(prev,next) switch_mm(prev, next, NULL)
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#endif
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@ -21,8 +21,6 @@
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#include <uapi/asm/ptrace.h>
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#define _PSR_PAN_BIT 22
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/* Current Exception Level values, as contained in CurrentEL */
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#define CurrentEL_EL1 (1 << 2)
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#define CurrentEL_EL2 (2 << 2)
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@ -29,9 +29,7 @@
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#include <asm/esr.h>
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#include <asm/irq.h>
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#include <asm/memory.h>
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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#include <asm/uaccess.h>
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#include <asm/unistd.h>
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/*
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@ -110,34 +108,6 @@
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mrs x22, elr_el1
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mrs x23, spsr_el1
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stp lr, x21, [sp, #S_LR]
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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/*
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* Set the TTBR0 PAN bit in SPSR. When the exception is taken from
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* EL0, there is no need to check the state of TTBR0_EL1 since
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* accesses are always enabled.
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* Note that the meaning of this bit differs from the ARMv8.1 PAN
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* feature as all TTBR0_EL1 accesses are disabled, not just those to
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* user mappings.
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*/
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alternative_if_not ARM64_HAS_PAN
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nop
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alternative_else
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b 1f // skip TTBR0 PAN
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alternative_endif
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.if \el != 0
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mrs x21, ttbr0_el1
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tst x21, #0xffff << 48 // Check for the reserved ASID
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orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
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b.eq 1f // TTBR0 access already disabled
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and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
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.endif
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uaccess_ttbr0_disable x21
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1:
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#endif
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stp x22, x23, [sp, #S_PC]
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/*
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@ -174,42 +144,6 @@ alternative_endif
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ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
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.if \el == 0
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ct_user_enter
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.endif
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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/*
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* Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
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* PAN bit checking.
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*/
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alternative_if_not ARM64_HAS_PAN
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nop
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alternative_else
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b 2f // skip TTBR0 PAN
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alternative_endif
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.if \el != 0
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tbnz x22, #_PSR_PAN_BIT, 1f // Skip re-enabling TTBR0 access if previously disabled
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.endif
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uaccess_ttbr0_enable x0
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.if \el == 0
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/*
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* Enable errata workarounds only if returning to user. The only
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* workaround currently required for TTBR0_EL1 changes are for the
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* Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
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* corruption).
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*/
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post_ttbr0_update_workaround
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.endif
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1:
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.if \el != 0
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and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
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.endif
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2:
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#endif
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.if \el == 0
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ldr x23, [sp, #S_SP] // load return stack pointer
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msr sp_el0, x23
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#ifdef CONFIG_ARM64_ERRATUM_845719
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@ -231,7 +165,6 @@ alternative_else
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alternative_endif
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#endif
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.endif
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msr elr_el1, x21 // set up the return data
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msr spsr_el1, x22
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ldp x0, x1, [sp, #16 * 0]
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@ -346,15 +346,6 @@ void __init setup_arch(char **cmdline_p)
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smp_init_cpus();
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smp_build_mpidr_hash();
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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/*
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* Make sure init_thread_info.ttbr0 always generates translation
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* faults in case uaccess_enable() is inadvertently called by the init
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* thread.
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*/
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init_thread_info.ttbr0 = virt_to_phys(empty_zero_page);
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#endif
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#ifdef CONFIG_VT
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#if defined(CONFIG_VGA_CONSOLE)
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conswitchp = &vga_con;
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@ -182,12 +182,7 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
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raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
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switch_mm_fastpath:
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/*
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* Defer TTBR0_EL1 setting for user threads to uaccess_enable() when
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* emulating PAN.
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*/
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if (!system_uses_ttbr0_pan())
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cpu_switch_mm(mm->pgd, mm);
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cpu_switch_mm(mm->pgd, mm);
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}
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static int asids_init(void)
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