clk: msm: clock-gpu-cobalt: Update the GPU PLL FMAXes
The clock driver only needs to put a MIN_SVS vote on the MX rail on behalf of the graphics PLLs. Update the fmax tables for the PLLs appropriately. CRs-Fixed: 1040775 Change-Id: Icb84b40128c54edefdec13f61fe9252811c1a14a Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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1 changed files with 6 additions and 6 deletions
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@ -109,7 +109,7 @@ static struct alpha_pll_clk gpu_pll0_pll = {
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.parent = &gpucc_xo.c,
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.parent = &gpucc_xo.c,
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.dbg_name = "gpu_pll0_pll",
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.dbg_name = "gpu_pll0_pll",
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.ops = &clk_ops_fabia_alpha_pll,
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.ops = &clk_ops_fabia_alpha_pll,
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VDD_GPU_PLL_FMAX_MAP1(NOMINAL, 1300000500),
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VDD_GPU_PLL_FMAX_MAP1(MIN, 1300000500),
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CLK_INIT(gpu_pll0_pll.c),
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CLK_INIT(gpu_pll0_pll.c),
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},
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},
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};
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};
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@ -168,7 +168,7 @@ static struct alpha_pll_clk gpu_pll1_pll = {
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.parent = &gpucc_xo.c,
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.parent = &gpucc_xo.c,
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.dbg_name = "gpu_pll1_pll",
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.dbg_name = "gpu_pll1_pll",
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.ops = &clk_ops_fabia_alpha_pll,
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.ops = &clk_ops_fabia_alpha_pll,
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VDD_GPU_PLL_FMAX_MAP1(NOMINAL, 1300000500),
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VDD_GPU_PLL_FMAX_MAP1(MIN, 1300000500),
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CLK_INIT(gpu_pll1_pll.c),
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CLK_INIT(gpu_pll1_pll.c),
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},
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},
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};
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};
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@ -670,15 +670,15 @@ static struct clk_lookup msm_clocks_gfxcc_cobalt[] = {
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static void msm_gfxcc_hamster_fixup(void)
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static void msm_gfxcc_hamster_fixup(void)
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{
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{
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gpu_pll0_pll.c.fmax[VDD_DIG_NOMINAL] = 1420000500;
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gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1420000500;
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gpu_pll1_pll.c.fmax[VDD_DIG_NOMINAL] = 1420000500;
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gpu_pll1_pll.c.fmax[VDD_DIG_MIN] = 1420000500;
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gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_vq;
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gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_vq;
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}
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}
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static void msm_gfxcc_cobalt_v2_fixup(void)
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static void msm_gfxcc_cobalt_v2_fixup(void)
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{
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{
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gpu_pll0_pll.c.fmax[VDD_DIG_NOMINAL] = 1420000500;
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gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1420000500;
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gpu_pll1_pll.c.fmax[VDD_DIG_NOMINAL] = 1420000500;
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gpu_pll1_pll.c.fmax[VDD_DIG_MIN] = 1420000500;
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gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_v2;
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gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_v2;
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}
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}
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