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ARM: dts: msm: add blsp devices config for msmcobalt

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Add device tree entries for i2c, spi, dma and uart.
All device entries are disabled by default and
allow to enable the required instances
in the main platform dtsi file.

Change-Id: I392bca629cfa87343f3a82ed13f48bafba592a51
Signed-off-by: Ankit Gupta <ankgupta@codeaurora.org>
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
This commit is contained in:
Ankit Gupta 2015-08-20 17:07:02 -06:00 • committed by Kyle Yan
parent e3b6c95c59
commit 8260b1194a
3 changed files with 1742 additions and 0 deletions
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861
arch/arm/boot/dts/qcom/msmcobalt-blsp.dtsi Normal file
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@ -0,0 +1,861 @@
/*
* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/ {
aliases {
i2c1 = &i2c_1;
i2c2 = &i2c_2;
i2c3 = &i2c_3;
i2c4 = &i2c_4;
i2c5 = &i2c_5;
i2c6 = &i2c_6;
i2c7 = &i2c_7;
i2c8 = &i2c_8;
i2c9 = &i2c_9;
i2c10 = &i2c_10;
i2c11 = &i2c_11;
i2c12 = &i2c_12;
spi1 = &spi_1;
spi2 = &spi_2;
spi3 = &spi_3;
spi4 = &spi_4;
spi5 = &spi_5;
spi6 = &spi_6;
spi7 = &spi_7;
spi8 = &spi_8;
spi9 = &spi_9;
spi10 = &spi_10;
spi11 = &spi_11;
spi12 = &spi_12;
};
};
#include "msmcobalt-pinctrl.dtsi"
&soc {
dma_blsp1: qcom,sps-dma@0xc144000 { /* BLSP1 */
#dma-cells = <4>;
compatible = "qcom,sps-dma";
reg = <0xc144000 0x25000>;
interrupts = <0 238 0>;
qcom,summing-threshold = <0x10>;
};
dma_blsp2: qcom,sps-dma@0xc184000 { /* BLSP2 */
#dma-cells = <4>;
compatible = "qcom,sps-dma";
reg = <0xc184000 0x25000>;
interrupts = <0 239 0>;
qcom,summing-threshold = <0x10>;
};
i2c_1: i2c@c175000 { /* BLSP1 QUP1 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC175000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 95 0>;
dmas = <&dma_blsp1 6 64 0x20000020 0x20>,
<&dma_blsp1 7 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <86>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_1_active>;
pinctrl-1 = <&i2c_1_sleep>;
status = "disabled";
};
i2c_2: i2c@c176000 { /* BLSP1 QUP2 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC176000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 96 0>;
dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
<&dma_blsp1 9 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <86>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_2_active>;
pinctrl-1 = <&i2c_2_sleep>;
status = "disabled";
};
i2c_3: i2c@c177000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC177000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 97 0>;
dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
<&dma_blsp1 11 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <86>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_3_active>;
pinctrl-1 = <&i2c_3_sleep>;
status = "disabled";
};
i2c_4: i2c@c178000 { /* BLSP1 QUP4 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC178000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 98 0>;
dmas = <&dma_blsp1 12 64 0x20000020 0x20>,
<&dma_blsp1 13 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <86>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_4_active>;
pinctrl-1 = <&i2c_4_sleep>;
status = "disabled";
};
i2c_5: i2c@c179000 { /* BLSP1 QUP5 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC179000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 99 0>;
dmas = <&dma_blsp1 14 64 0x20000020 0x20>,
<&dma_blsp1 15 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <86>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_5_active>;
pinctrl-1 = <&i2c_5_sleep>;
status = "disabled";
};
i2c_6: i2c@c17a000 { /* BLSP1 QUP6 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC17A000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 100 0>;
dmas = <&dma_blsp1 16 64 0x20000020 0x20>,
<&dma_blsp1 17 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <86>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup6_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_6_active>;
pinctrl-1 = <&i2c_6_sleep>;
status = "disabled";
};
i2c_7: i2c@c1b5000 { /* BLSP2 QUP1 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC1B5000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 101 0>;
dmas = <&dma_blsp2 6 64 0x20000020 0x20>,
<&dma_blsp2 7 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <84>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup1_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_7_active>;
pinctrl-1 = <&i2c_7_sleep>;
status = "disabled";
};
i2c_8: i2c@c1b6000 { /* BLSP2 QUP2 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC1B6000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 102 0>;
dmas = <&dma_blsp2 8 64 0x20000020 0x20>,
<&dma_blsp2 9 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <84>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup2_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_8_active>;
pinctrl-1 = <&i2c_8_sleep>;
status = "disabled";
};
i2c_9: i2c@c1b7000 { /* BLSP2 QUP3 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC1B7000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 103 0>;
dmas = <&dma_blsp2 10 64 0x20000020 0x20>,
<&dma_blsp2 11 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <84>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup3_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_9_active>;
pinctrl-1 = <&i2c_9_sleep>;
status = "disabled";
};
i2c_10: i2c@c1b8000 { /* BLSP2 QUP4 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC1B8000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 104 0>;
dmas = <&dma_blsp2 12 64 0x20000020 0x20>,
<&dma_blsp2 13 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <84>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup4_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_10_active>;
pinctrl-1 = <&i2c_10_sleep>;
status = "disabled";
};
i2c_11: i2c@c1b9000 { /* BLSP2 QUP5 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC1B9000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 105 0>;
dmas = <&dma_blsp2 14 64 0x20000020 0x20>,
<&dma_blsp2 15 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <84>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup5_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_11_active>;
pinctrl-1 = <&i2c_11_sleep>;
status = "disabled";
};
i2c_12: i2c@c1ba000 { /* BLSP2 QUP6 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0xC1BA000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 106 0>;
dmas = <&dma_blsp2 16 64 0x20000020 0x20>,
<&dma_blsp2 17 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <84>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup6_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_12_active>;
pinctrl-1 = <&i2c_12_sleep>;
status = "disabled";
};
spi_1: spi@c175000 { /* BLSP1 QUP1 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC175000 0x600>,
<0xC144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 95 0>, <0 238 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <6>;
qcom,bam-producer-pipe-index = <7>;
qcom,master-id = <86>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_1_active>;
pinctrl-1 = <&spi_1_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>;
status = "disabled";
};
spi_2: spi@c176000 { /* BLSP1 QUP2 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC176000 0x600>,
<0xC144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 96 0>, <0 238 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <8>;
qcom,bam-producer-pipe-index = <9>;
qcom,master-id = <86>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_2_active>;
pinctrl-1 = <&spi_2_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>;
status = "disabled";
};
spi_3: spi@c177000 { /* BLSP1 QUP3 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC177000 0x600>,
<0xC144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 97 0>, <0 238 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <10>;
qcom,bam-producer-pipe-index = <11>;
qcom,master-id = <86>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_3_active>;
pinctrl-1 = <&spi_3_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>;
status = "disabled";
};
spi_4: spi@c178000 { /* BLSP1 QUP4 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC178000 0x600>,
<0xC144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 98 0>, <0 238 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <12>;
qcom,bam-producer-pipe-index = <13>;
qcom,master-id = <86>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_4_active>;
pinctrl-1 = <&spi_4_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup4_spi_apps_clk>;
status = "disabled";
};
spi_5: spi@c179000 { /* BLSP1 QUP5 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC179000 0x600>,
<0xC144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 99 0>, <0 238 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <14>;
qcom,bam-producer-pipe-index = <15>;
qcom,master-id = <86>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_5_active>;
pinctrl-1 = <&spi_5_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup5_spi_apps_clk>;
status = "disabled";
};
spi_6: spi@c17a000 { /* BLSP1 QUP6 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC17A000 0x600>,
<0xC144000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 100 0>, <0 238 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <16>;
qcom,bam-producer-pipe-index = <17>;
qcom,master-id = <86>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_6_active>;
pinctrl-1 = <&spi_6_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup6_spi_apps_clk>;
status = "disabled";
};
spi_7: spi@c1b5000 { /* BLSP2 QUP1 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC1B5000 0x600>,
<0xC184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 101 0>, <0 239 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <6>;
qcom,bam-producer-pipe-index = <7>;
qcom,master-id = <84>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_7_active>;
pinctrl-1 = <&spi_7_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup1_spi_apps_clk>;
status = "disabled";
};
spi_8: spi@c1b6000 { /* BLSP2 QUP2 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC1B6000 0x600>,
<0xC184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 102 0>, <0 239 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <8>;
qcom,bam-producer-pipe-index = <9>;
qcom,master-id = <84>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_8_active>;
pinctrl-1 = <&spi_8_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup2_spi_apps_clk>;
status = "disabled";
};
spi_9: spi@c1b7000 { /* BLSP2 QUP3 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC1B7000 0x600>,
<0xC184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 103 0>, <0 239 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <10>;
qcom,bam-producer-pipe-index = <11>;
qcom,master-id = <84>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_9_active>;
pinctrl-1 = <&spi_9_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup3_spi_apps_clk>;
status = "disabled";
};
spi_10: spi@c1b8000 { /* BLSP2 QUP4 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC1B8000 0x600>,
<0xC184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 104 0>, <0 239 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <12>;
qcom,bam-producer-pipe-index = <13>;
qcom,master-id = <84>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_10_active>;
pinctrl-1 = <&spi_10_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup4_spi_apps_clk>;
status = "disabled";
};
spi_11: spi@c1b9000 { /* BLSP2 QUP5 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC1B9000 0x600>,
<0xC184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 105 0>, <0 239 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <14>;
qcom,bam-producer-pipe-index = <15>;
qcom,master-id = <84>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_11_active>;
pinctrl-1 = <&spi_11_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup5_spi_apps_clk>;
status = "disabled";
};
spi_12: spi@c1ba000 { /* BLSP2 QUP6 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xC1BA000 0x600>,
<0xC184000 0x25000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 106 0>, <0 239 0>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <16>;
qcom,bam-producer-pipe-index = <17>;
qcom,master-id = <84>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_12_active>;
pinctrl-1 = <&spi_12_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup6_spi_apps_clk>;
status = "disabled";
};
blsp1_uart1_hs: uart@c16f000 { /* BLSP1 UART1 */
compatible = "qcom,msm-hsuart-v14";
reg = <0xC16F000 0x200>,
<0xC144000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp1_uart1_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 0 107 0
1 &intc 0 0 238 0
2 &tlmm 1 0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xFD>;
qcom,bam-tx-ep-pipe-index = <0>;
qcom,bam-rx-ep-pipe-index = <1>;
qcom,master-id = <86>;
clock-names = "core_clk", "iface_clk";
clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart1_sleep>;
pinctrl-1 = <&blsp1_uart1_active>;
qcom,msm-bus,name = "buart1";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<86 512 0 0>,
<86 512 500 800>;
status = "disabled";
};
blsp1_uart2_hs: uart@c170000 { /* BLSP1 UART2 */
compatible = "qcom,msm-hsuart-v14";
reg = <0xC170000 0x200>,
<0xC144000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp1_uart2_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 0 108 0
1 &intc 0 0 238 0
2 &tlmm 5 0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xFD>;
qcom,bam-tx-ep-pipe-index = <2>;
qcom,bam-rx-ep-pipe-index = <3>;
qcom,master-id = <86>;
clock-names = "core_clk", "iface_clk";
clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart2_sleep>;
pinctrl-1 = <&blsp1_uart2_active>;
qcom,msm-bus,name = "buart2";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<86 512 0 0>,
<86 512 500 800>;
status = "disabled";
};
blsp1_uart3_hs: uart@c171000 { /* BLSP1 UART3 */
compatible = "qcom,msm-hsuart-v14";
reg = <0xC171000 0x200>,
<0xC144000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp1_uart3_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 0 109 0
1 &intc 0 0 238 0
2 &tlmm 9 0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xFD>;
qcom,bam-tx-ep-pipe-index = <4>;
qcom,bam-rx-ep-pipe-index = <5>;
qcom,master-id = <86>;
clock-names = "core_clk", "iface_clk";
clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>,
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart3_sleep>;
pinctrl-1 = <&blsp1_uart3_active>;
qcom,msm-bus,name = "buart3";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<86 512 0 0>,
<86 512 500 800>;
status = "disabled";
};
blsp2_uart1_hs: uart@c1af000 { /* BLSP2 UART1 */
compatible = "qcom,msm-hsuart-v14";
reg = <0xC1AF000 0x200>,
<0xC184000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp2_uart1_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 0 113 0
1 &intc 0 0 239 0
2 &tlmm 1 0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xFD>;
qcom,bam-tx-ep-pipe-index = <0>;
qcom,bam-rx-ep-pipe-index = <1>;
qcom,master-id = <84>;
clock-names = "core_clk", "iface_clk";
clocks = <&clock_gcc clk_gcc_blsp2_uart1_apps_clk>,
<&clock_gcc clk_gcc_blsp2_ahb_clk>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp2_uart1_sleep>;
pinctrl-1 = <&blsp2_uart1_active>;
qcom,msm-bus,name = "buart1";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<86 512 0 0>,
<86 512 500 800>;
status = "disabled";
};
blsp2_uart2_hs: uart@c1b0000 { /* BLSP2 UART2 */
compatible = "qcom,msm-hsuart-v14";
reg = <0xC1B0000 0x200>,
<0xC184000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp2_uart2_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 0 114 0
1 &intc 0 0 239 0
2 &tlmm 5 0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xFD>;
qcom,bam-tx-ep-pipe-index = <2>;
qcom,bam-rx-ep-pipe-index = <3>;
qcom,master-id = <84>;
clock-names = "core_clk", "iface_clk";
clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>,
<&clock_gcc clk_gcc_blsp2_ahb_clk>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp2_uart2_sleep>;
pinctrl-1 = <&blsp2_uart2_active>;
qcom,msm-bus,name = "buart2";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<86 512 0 0>,
<86 512 500 800>;
status = "disabled";
};
blsp2_uart3_hs: uart@c1b1000 { /* BLSP2 UART3 */
compatible = "qcom,msm-hsuart-v14";
reg = <0xC1B1000 0x200>,
<0xC184000 0x25000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp2_uart3_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 0 115 0
1 &intc 0 0 239 0
2 &tlmm 9 0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xFD>;
qcom,bam-tx-ep-pipe-index = <4>;
qcom,bam-rx-ep-pipe-index = <5>;
qcom,master-id = <84>;
clock-names = "core_clk", "iface_clk";
clocks = <&clock_gcc clk_gcc_blsp2_uart3_apps_clk>,
<&clock_gcc clk_gcc_blsp2_ahb_clk>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp2_uart3_sleep>;
pinctrl-1 = <&blsp2_uart3_active>;
qcom,msm-bus,name = "buart3";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<86 512 0 0>,
<86 512 500 800>;
status = "disabled";
};
};

880
arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi
View file

@ -49,6 +49,441 @@
};
};
/* I2C CONFIGURATION */
i2c_1 {
i2c_1_active: i2c_1_active {
mux {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
};
config {
pins = "gpio2", "gpio3";
drive-strength = <2>;
bias-disable;
};
};
i2c_1_sleep: i2c_1_sleep {
mux {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
};
config {
pins = "gpio2", "gpio3";
drive-strength = <2>;
bias-pull-up;
};
};
};
i2c_2 {
i2c_2_active: i2c_2_active {
mux {
pins = "gpio32", "gpio33";
function = "blsp_i2c2";
};
config {
pins = "gpio32", "gpio33";
drive-strength = <2>;
bias-disable;
};
};
i2c_2_sleep: i2c_2_sleep {
mux {
pins = "gpio32", "gpio33";
function = "blsp_i2c2";
};
config {
pins = "gpio32", "gpio33";
drive-strength = <2>;
bias-pull-up;
};
};
};
i2c_3 {
i2c_3_active: i2c_3_active {
mux {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
};
config {
pins = "gpio47", "gpio48";
drive-strength = <2>;
bias-disable;
};
};
i2c_3_sleep: i2c_3_sleep {
mux {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
};
config {
pins = "gpio47", "gpio48";
drive-strength = <2>;
bias-pull-up;
};
};
};
i2c_4 {
i2c_4_active: i2c_4_active {
mux {
pins = "gpio10", "gpio11";
function = "blsp_i2c4";
};
config {
pins = "gpio10", "gpio11";
drive-strength = <2>;
bias-disable;
};
};
i2c_4_sleep: i2c_4_sleep {
mux {
pins = "gpio10", "gpio11";
function = "blsp_i2c4";
};
config {
pins = "gpio10", "gpio11";
drive-strength = <2>;
bias-pull-up;
};
};
};
i2c_5 {
i2c_5_active: i2c_5_active {
mux {
pins = "gpio87", "gpio88";
function = "blsp_i2c5";
};
config {
pins = "gpio87", "gpio88";
drive-strength = <2>;
bias-disable;
};
};
i2c_5_sleep: i2c_5_sleep {
mux {
pins = "gpio87", "gpio88";
function = "blsp_i2c5";
};
config {
pins = "gpio87", "gpio88";
drive-strength = <2>;
bias-pull-up;
};
};
};
i2c_6 {
i2c_6_active: i2c_6_active {
mux {
pins = "gpio43", "gpio44";
function = "blsp_i2c6";
};
config {
pins = "gpio43", "gpio44";
drive-strength = <2>;
bias-disable;
};
};
i2c_6_sleep: i2c_6_sleep {
mux {
pins = "gpio43", "gpio44";
function = "blsp_i2c6";
};
config {
pins = "gpio43", "gpio44";
drive-strength = <2>;
bias-pull-up;
};
};
};
i2c_7 {
i2c_7_active: i2c_7_active {
mux {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
};
config {
pins = "gpio55", "gpio56";
drive-strength = <2>;
bias-disable;
};
};
i2c_7_sleep: i2c_7_sleep {
mux {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
};
config {
pins = "gpio55", "gpio56";
drive-strength = <2>;
bias-pull-up;
};
};
};
i2c_8 {
i2c_8_active: i2c_8_active {
mux {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
};
config {
pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
};
i2c_8_sleep: i2c_8_sleep {
mux {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
};
config {
pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-pull-up;
};
};
};
i2c_9 {
i2c_9_active: i2c_9_active {
mux {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
};
config {
pins = "gpio51", "gpio52";
drive-strength = <2>;
bias-disable;
};
};
i2c_9_sleep: i2c_9_sleep {
mux {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
};
config {
pins = "gpio51", "gpio52";
drive-strength = <2>;
bias-pull-up;
};
};
};
i2c_10 {
i2c_10_active: i2c_10_active {
mux {
pins = "gpio67", "gpio68";
function = "blsp_i2c10";
};
config {
pins = "gpio67", "gpio68";
drive-strength = <2>;
bias-disable;
};
};
i2c_10_sleep: i2c_10_sleep {
mux {
pins = "gpio67", "gpio68";
function = "blsp_i2c10";
};
config {
pins = "gpio67", "gpio68";
drive-strength = <2>;
bias-pull-up;
};
};
};
i2c_11 {
i2c_11_active: i2c_11_active {
mux {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
};
config {
pins = "gpio60", "gpio61";
drive-strength = <2>;
bias-disable;
};
};
i2c_11_sleep: i2c_11_sleep {
mux {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
};
config {
pins = "gpio60", "gpio61";
drive-strength = <2>;
bias-pull-up;
};
};
};
i2c_12 {
i2c_12_active: i2c_12_active {
mux {
pins = "gpio83", "gpio84";
function = "blsp_i2c12";
};
config {
pins = "gpio83", "gpio84";
drive-strength = <2>;
bias-disable;
};
};
i2c_12_sleep: i2c_12_sleep {
mux {
pins = "gpio83", "gpio84";
function = "blsp_i2c12";
};
config {
pins = "gpio83", "gpio84";
drive-strength = <2>;
bias-pull-up;
};
};
};
/* SPI CONFIGURATION */
spi_1 {
spi_1_active: spi_1_active {
mux {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
function = "blsp_spi1";
};
config {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
drive-strength = <6>;
bias-disable;
};
};
spi_1_sleep: spi_1_sleep {
mux {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
function = "blsp_spi1";
};
config {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
drive-strength = <6>;
bias-disable;
};
};
};
spi_2 {
spi_2_active: spi_2_active {
mux {
pins = "gpio31", "gpio34",
"gpio32", "gpio33";
function = "blsp_spi2";
};
config {
pins = "gpio31", "gpio34",
"gpio32", "gpio33";
drive-strength = <6>;
bias-disable;
};
};
spi_2_sleep: spi_2_sleep {
mux {
pins = "gpio31", "gpio34",
"gpio32", "gpio33";
function = "blsp_spi2";
};
config {
pins = "gpio31", "gpio34",
"gpio32", "gpio33";
drive-strength = <6>;
bias-disable;
};
};
};
spi_3 {
spi_3_active: spi_3_active {
mux {
pins = "gpio45", "gpio46",
"gpio47", "gpio48";
function = "blsp_spi3";
};
config {
pins = "gpio45", "gpio46",
"gpio47", "gpio48";
drive-strength = <6>;
bias-disable;
};
};
spi_3_sleep: spi_3_sleep {
mux {
pins = "gpio45", "gpio46",
"gpio47", "gpio48";
function = "blsp_spi3";
};
config {
pins = "gpio45", "gpio46",
"gpio47", "gpio48";
drive-strength = <6>;
bias-disable;
};
};
};
cdc_reset_ctrl {
cdc_reset_sleep: cdc_reset_sleep {
mux {
@ -76,6 +511,38 @@
};
};
spi_4 {
spi_4_active: spi_4_active {
mux {
pins = "gpio8", "gpio9",
"gpio10", "gpio1";
function = "blsp_spi4";
};
config {
pins = "gpio8", "gpio9",
"gpio10", "gpio1";
drive-strength = <6>;
bias-disable;
};
};
spi_4_sleep: spi_4_sleep {
mux {
pins = "gpio8", "gpio9",
"gpio10", "gpio1";
function = "blsp_spi4";
};
config {
pins = "gpio8", "gpio9",
"gpio10", "gpio1";
drive-strength = <6>;
bias-disable;
};
};
};
spkr_1_sd_n {
spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
mux {
@ -103,6 +570,38 @@
};
};
spi_5 {
spi_5_active: spi_5_active {
mux {
pins = "gpio0", "gpio",
"gpio2", "gpio3";
function = "blsp_spi5";
};
config {
pins = "gpio85", "gpio86",
"gpio87", "gpio88";
drive-strength = <6>;
bias-disable;
};
};
spi_5_sleep: spi_5_sleep {
mux {
pins = "gpio85", "gpio86",
"gpio87", "gpio88";
function = "blsp_spi5";
};
config {
pins = "gpio85", "gpio86",
"gpio87", "gpio88";
drive-strength = <6>;
bias-disable;
};
};
};
spkr_2_sd_n {
spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
mux {
@ -258,6 +757,257 @@
};
};
spi_6 {
spi_6_active: spi_6_active {
mux {
pins = "gpio41", "gpio42",
"gpio43", "gpio44";
function = "blsp_spi6";
};
config {
pins = "gpio41", "gpio42",
"gpio43", "gpio44";
drive-strength = <6>;
bias-disable;
};
};
spi_6_sleep: spi_6_sleep {
mux {
pins = "gpio41", "gpio42",
"gpio43", "gpio44";
function = "blsp_spi6";
};
config {
pins = "gpio41", "gpio42",
"gpio43", "gpio44";
drive-strength = <6>;
bias-disable;
};
};
};
spi_7 {
spi_7_active: spi_7_active {
mux {
pins = "gpio53", "gpio54",
"gpio55", "gpio56";
function = "blsp_spi7";
};
config {
pins = "gpio53", "gpio54",
"gpio55", "gpio56";
drive-strength = <6>;
bias-disable;
};
};
spi_7_sleep: spi_7_sleep {
mux {
pins = "gpio53", "gpio54",
"gpio55", "gpio56";
function = "blsp_spi7";
};
config {
pins = "gpio53", "gpio54",
"gpio55", "gpio56";
drive-strength = <6>;
bias-disable;
};
};
};
spi_8 {
spi_8_active: spi_8_active {
mux {
pins = "gpio4", "gpio5",
"gpio6", "gpio7";
function = "blsp_spi8";
};
config {
pins = "gpio4", "gpio5",
"gpio6", "gpio7";
drive-strength = <6>;
bias-disable;
};
};
spi_8_sleep: spi_8_sleep {
mux {
pins = "gpio4", "gpio5",
"gpio6", "gpio7";
function = "blsp_spi8";
};
config {
pins = "gpio4", "gpio5",
"gpio6", "gpio7";
drive-strength = <6>;
bias-disable;
};
};
};
spi_9 {
spi_9_active: spi_9_active {
mux {
pins = "gpio49", "gpio50",
"gpio51", "gpio52";
function = "blsp_spi9";
};
config {
pins = "gpio49", "gpio50",
"gpio51", "gpio52";
drive-strength = <6>;
bias-disable;
};
};
spi_9_sleep: spi_9_sleep {
mux {
pins = "gpio49", "gpio50",
"gpio51", "gpio52";
function = "blsp_spi9";
};
config {
pins = "gpio49", "gpio50",
"gpio51", "gpio52";
drive-strength = <6>;
bias-disable;
};
};
};
spi_10 {
spi_10_active: spi_10_active {
mux {
pins = "gpio65", "gpio66",
"gpio67", "gpio68";
function = "blsp_spi10";
};
config {
pins = "gpio65", "gpio66",
"gpio67", "gpio68";
drive-strength = <6>;
bias-disable;
};
};
spi_10_sleep: spi_10_sleep {
mux {
pins = "gpio65", "gpio66",
"gpio67", "gpio68";
function = "blsp_spi10";
};
config {
pins = "gpio65", "gpio66",
"gpio67", "gpio68";
drive-strength = <6>;
bias-disable;
};
};
};
spi_11 {
spi_11_active: spi_11_active {
mux {
pins = "gpio58", "gpio59",
"gpio60", "gpio61";
function = "blsp_spi11";
};
config {
pins = "gpio58", "gpio59",
"gpio60", "gpio61";
drive-strength = <6>;
bias-disable;
};
};
spi_11_sleep: spi_11_sleep {
mux {
pins = "gpio58", "gpio59",
"gpio60", "gpio61";
function = "blsp_spi11";
};
config {
pins = "gpio58", "gpio59",
"gpio60", "gpio61";
drive-strength = <6>;
bias-disable;
};
};
};
spi_12 {
spi_12_active: spi_12_active {
mux {
pins = "gpio81", "gpio82",
"gpio83", "gpio84";
function = "blsp_spi12";
};
config {
pins = "gpio81", "gpio82",
"gpio83", "gpio84";
drive-strength = <6>;
bias-disable;
};
};
spi_12_sleep: spi_12_sleep {
mux {
pins = "gpio81", "gpio82",
"gpio83", "gpio84";
function = "blsp_spi12";
};
config {
pins = "gpio81", "gpio82",
"gpio83", "gpio84";
drive-strength = <6>;
bias-disable;
};
};
};
/* HS UART CONFIGURATION */
blsp1_uart1_active: blsp1_uart1_active {
mux {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "blsp_uart1_a";
};
config {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
drive-strength = <2>;
bias-disable;
};
};
blsp1_uart1_sleep: blsp1_uart1_sleep {
mux {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "gpio";
};
config {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
drive-strength = <2>;
bias-disable;
};
};
cam_sensor_rear_suspend: cam_sensor_rear_suspend {
/* RESET, STANDBY */
mux {
@ -316,6 +1066,58 @@
};
};
blsp1_uart2_active: blsp1_uart2_active {
mux {
pins = "gpio31", "gpio34", "gpio33", "gpio32";
function = "blsp_uart2_a";
};
config {
pins = "gpio31", "gpio34", "gpio33", "gpio32";
drive-strength = <2>;
bias-disable;
};
};
blsp1_uart2_sleep: blsp1_uart2_sleep {
mux {
pins = "gpio31", "gpio34", "gpio33", "gpio32";
function = "gpio";
};
config {
pins = "gpio31", "gpio34", "gpio33", "gpio32";
drive-strength = <2>;
bias-disable;
};
};
blsp1_uart3_active: blsp1_uart3_active {
mux {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "blsp_uart3_a";
};
config {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
drive-strength = <2>;
bias-disable;
};
};
blsp1_uart3_sleep: blsp1_uart3_sleep {
mux {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "gpio";
};
config {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
drive-strength = <2>;
bias-disable;
};
};
cam_sensor_rear2_sus {
cam_sensor_rear2_suspend: cam_sensor_rear2_suspend {
/* RESET, STANDBY */
@ -376,6 +1178,58 @@
};
};
blsp2_uart1_active: blsp2_uart1_active {
mux {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
function = "blsp_uart7_a";
};
config {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
drive-strength = <2>;
bias-disable;
};
};
blsp2_uart1_sleep: blsp2_uart1_sleep {
mux {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
function = "gpio";
};
config {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
drive-strength = <2>;
bias-disable;
};
};
blsp2_uart2_active: blsp2_uart2_active {
mux {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "blsp_uart8_a";
};
config {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
};
blsp2_uart2_sleep: blsp2_uart2_sleep {
mux {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "gpio";
};
config {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
};
cam_sensor_front_suspend: cam_sensor_front_suspend {
/* RESET, STANDBY */
mux {
@ -442,5 +1296,31 @@
};
};
};
blsp2_uart3_active: blsp2_uart3_active {
mux {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_uart9_a";
};
config {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
drive-strength = <2>;
bias-disable;
};
};
blsp2_uart3_sleep: blsp2_uart3_sleep {
mux {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "gpio";
};
config {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
drive-strength = <2>;
bias-disable;
};
};
};
};

1
arch/arm/boot/dts/qcom/msmcobalt.dtsi
View file

@ -2294,3 +2294,4 @@
#include "msmcobalt-audio.dtsi"
#include "msmcobalt-mdss.dtsi"
#include "msmcobalt-mdss-pll.dtsi"
#include "msmcobalt-blsp.dtsi"