clk: msm: hdmi: add support for live programming of HDMI PLL
Clock recovery and dynamic resolution change require changing HDMI clock rate while HDMI PLL is on. There are two paths while clock is changed, one is atomic update which doesn't require PLL tear down, the other is when clock rate change is too big and a full PLL tear down is needed. CRs-Fixed: 1086894 Change-Id: Ia202e0aee09f506a7bbe4e13702f30dee119ce8e Signed-off-by: Ray Zhang <rayz@codeaurora.org>
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Ray Zhang
parent
bee274711e
commit
83c88144ae
1 changed files with 145 additions and 43 deletions
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@ -29,6 +29,7 @@
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#define _R(x, y) MDSS_PLL_REG_R(x, y)
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/* PLL REGISTERS */
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#define FREQ_UPDATE (0x008)
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#define BIAS_EN_CLKBUFLR_EN (0x034)
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#define CLK_ENABLE1 (0x038)
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#define SYS_CLK_CTRL (0x03C)
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@ -80,6 +81,7 @@
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#define HDMI_BIT_CLK_TO_PIX_CLK_RATIO 10
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#define HDMI_MHZ_TO_HZ 1000000
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#define HDMI_HZ_TO_MHZ 1000000
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#define HDMI_KHZ_TO_HZ 1000
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#define HDMI_REF_CLOCK_MHZ 19.2
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#define HDMI_REF_CLOCK_HZ (HDMI_REF_CLOCK_MHZ * 1000000)
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#define HDMI_VCO_MIN_RATE_HZ 25000000
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@ -609,49 +611,6 @@ static int hdmi_8998_phy_ready_status(struct mdss_pll_resources *io)
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return rc;
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}
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static int hdmi_8998_vco_set_rate(struct clk *c, unsigned long rate)
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{
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int rc = 0;
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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struct mdss_pll_resources *io = vco->priv;
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rc = mdss_pll_resource_enable(io, true);
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if (rc) {
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pr_err("pll resource enable failed, rc=%d\n", rc);
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return rc;
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}
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if (io->pll_on)
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goto error;
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rc = hdmi_8998_pll_set_clk_rate(c, rate);
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if (rc) {
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pr_err("failed to set clk rate, rc=%d\n", rc);
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goto error;
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}
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vco->rate = rate;
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vco->rate_set = true;
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error:
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(void)mdss_pll_resource_enable(io, false);
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return rc;
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}
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static long hdmi_8998_vco_round_rate(struct clk *c, unsigned long rate)
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{
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unsigned long rrate = rate;
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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if (rate < vco->min_rate)
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rrate = vco->min_rate;
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if (rate > vco->max_rate)
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rrate = vco->max_rate;
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return rrate;
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}
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static int hdmi_8998_pll_enable(struct clk *c)
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{
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int rc = 0;
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@ -700,6 +659,149 @@ static int hdmi_8998_pll_enable(struct clk *c)
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return rc;
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}
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/*
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* Get the clock range allowed in atomic update. If clock rate
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* goes beyond this range, a full tear down is required to set
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* the new pixel clock.
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*/
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static int hdmi_8998_vco_get_lock_range(struct clk *c,
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unsigned long pixel_clk)
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{
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const u32 rng = 64, cmp_cnt = 1024;
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const u32 coreclk_div = 5, clks_pll_divsel = 2;
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u32 vco_freq, vco_ratio, ppm_range;
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struct hdmi_8998_reg_cfg cfg = {0};
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pr_debug("rate=%ld\n", pixel_clk);
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hdmi_8998_get_div(&cfg, pixel_clk);
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if (cfg.vco_ratio <= 0 || cfg.vco_freq <= 0) {
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pr_err("couldn't get post div\n");
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return -EINVAL;
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}
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vco_freq = (u32) cfg.vco_freq;
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vco_ratio = (u32) cfg.vco_ratio;
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pr_debug("freq %d, ratio %d\n", vco_freq, vco_ratio);
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ppm_range = (rng * HDMI_REF_CLOCK_HZ) / cmp_cnt;
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ppm_range /= vco_freq / vco_ratio;
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ppm_range *= coreclk_div * clks_pll_divsel;
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pr_debug("ppm range: %d\n", ppm_range);
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return ppm_range;
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}
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static int hdmi_8998_vco_rate_atomic_update(struct clk *c,
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unsigned long rate)
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{
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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struct mdss_pll_resources *io = vco->priv;
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void __iomem *pll;
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struct hdmi_8998_reg_cfg cfg = {0};
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int rc = 0;
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rc = hdmi_8998_config_phy(rate, &cfg);
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if (rc) {
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pr_err("rate calculation failed\n, rc=%d", rc);
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goto end;
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}
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pll = io->pll_base;
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_W(pll, DEC_START_MODE0, cfg.dec_start_mode0);
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_W(pll, DIV_FRAC_START1_MODE0, cfg.div_frac_start1_mode0);
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_W(pll, DIV_FRAC_START2_MODE0, cfg.div_frac_start2_mode0);
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_W(pll, DIV_FRAC_START3_MODE0, cfg.div_frac_start3_mode0);
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_W(pll, FREQ_UPDATE, 0x01);
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_W(pll, FREQ_UPDATE, 0x00);
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pr_debug("updated to rate %ld\n", rate);
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end:
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return rc;
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}
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static int hdmi_8998_vco_set_rate(struct clk *c, unsigned long rate)
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{
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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struct mdss_pll_resources *io = vco->priv;
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unsigned int set_power_dwn = 0;
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bool atomic_update = false;
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int pll_lock_range = 0;
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int rc = 0;
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rc = mdss_pll_resource_enable(io, true);
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if (rc) {
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pr_err("pll resource enable failed, rc=%d\n", rc);
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return rc;
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}
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pr_debug("rate %ld\n", rate);
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if (_R(io->pll_base, C_READY_STATUS) & BIT(0) &&
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_R(io->phy_base, PHY_STATUS) & BIT(0)) {
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pll_lock_range = hdmi_8998_vco_get_lock_range(c, vco->rate);
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if (pll_lock_range > 0 && vco->rate) {
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u32 range_limit;
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range_limit = vco->rate *
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(pll_lock_range / HDMI_KHZ_TO_HZ);
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range_limit /= HDMI_KHZ_TO_HZ;
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pr_debug("range limit %d\n", range_limit);
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if (abs(rate - vco->rate) < range_limit)
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atomic_update = true;
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}
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}
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if (io->pll_on && !atomic_update)
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set_power_dwn = 1;
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if (atomic_update)
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rc = hdmi_8998_vco_rate_atomic_update(c, rate);
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else
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rc = hdmi_8998_pll_set_clk_rate(c, rate);
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if (rc) {
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pr_err("failed to set clk rate\n");
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goto error;
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}
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if (set_power_dwn) {
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rc = hdmi_8998_pll_enable(c);
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if (rc) {
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pr_err("failed to enable pll, rc=%d\n", rc);
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goto error;
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}
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}
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vco->rate = rate;
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vco->rate_set = true;
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error:
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(void)mdss_pll_resource_enable(io, false);
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return rc;
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}
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static long hdmi_8998_vco_round_rate(struct clk *c, unsigned long rate)
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{
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unsigned long rrate = rate;
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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if (rate < vco->min_rate)
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rrate = vco->min_rate;
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if (rate > vco->max_rate)
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rrate = vco->max_rate;
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return rrate;
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}
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static int hdmi_8998_vco_prepare(struct clk *c)
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{
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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