evie/android_kernel_oneplus_msm8998
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cxgb4: Remove duplicate register definitions

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Removed duplicate definition for SGE_PF_KDOORBELL, SGE_INT_ENABLE3,
PCIE_MEM_ACCESS_OFFSET registers.
Moved the register field definitions around the register definition.

Signed-off-by: Santosh Rastapur <santosh@chelsio.com>
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Reviewed-by: Sivakumar Subramani <sivasu@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vipul Pandya 2012-09-05 02:01:55 +00:00 • committed by David S. Miller
parent e5619c120d
commit 840f300025
4 changed files with 30 additions and 58 deletions
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18
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
View file

@ -2470,8 +2470,8 @@ int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
else else
delta = size - hw_pidx + pidx; delta = size - hw_pidx + pidx;
wmb(); wmb();
t4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL), t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
V_QID(qid) | V_PIDX(delta)); QID(qid) | PIDX(delta));
} }
out: out:
return ret; return ret;
@ -2579,8 +2579,8 @@ static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
else else
delta = q->size - hw_pidx + q->db_pidx; delta = q->size - hw_pidx + q->db_pidx;
wmb(); wmb();
t4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL), t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
V_QID(q->cntxt_id) | V_PIDX(delta)); QID(q->cntxt_id) | PIDX(delta));
} }
out: out:
q->db_disabled = 0; q->db_disabled = 0;
@ -2617,9 +2617,9 @@ static void process_db_full(struct work_struct *work)
notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
drain_db_fifo(adap, dbfifo_drain_delay); drain_db_fifo(adap, dbfifo_drain_delay);
t4_set_reg_field(adap, A_SGE_INT_ENABLE3, t4_set_reg_field(adap, SGE_INT_ENABLE3,
F_DBFIFO_HP_INT | F_DBFIFO_LP_INT, DBFIFO_HP_INT | DBFIFO_LP_INT,
F_DBFIFO_HP_INT | F_DBFIFO_LP_INT); DBFIFO_HP_INT | DBFIFO_LP_INT);
notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
} }
@ -2639,8 +2639,8 @@ static void process_db_drop(struct work_struct *work)
void t4_db_full(struct adapter *adap) void t4_db_full(struct adapter *adap)
{ {
t4_set_reg_field(adap, A_SGE_INT_ENABLE3, t4_set_reg_field(adap, SGE_INT_ENABLE3,
F_DBFIFO_HP_INT | F_DBFIFO_LP_INT, 0); DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
queue_work(workq, &adap->db_full_task); queue_work(workq, &adap->db_full_task);
} }

4
drivers/net/ethernet/chelsio/cxgb4/sge.c
View file

@ -769,8 +769,8 @@ static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
wmb(); /* write descriptors before telling HW */ wmb(); /* write descriptors before telling HW */
spin_lock(&q->db_lock); spin_lock(&q->db_lock);
if (!q->db_disabled) { if (!q->db_disabled) {
t4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL), t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
V_QID(q->cntxt_id) | V_PIDX(n)); QID(q->cntxt_id) | PIDX(n));
} }
q->db_pidx = q->pidx; q->db_pidx = q->pidx;
spin_unlock(&q->db_lock); spin_unlock(&q->db_lock);

12
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
View file

@ -1018,9 +1018,9 @@ static void sge_intr_handler(struct adapter *adapter)
{ ERR_INVALID_CIDX_INC, { ERR_INVALID_CIDX_INC,
"SGE GTS CIDX increment too large", -1, 0 }, "SGE GTS CIDX increment too large", -1, 0 },
{ ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
{ F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full }, { DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
{ F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full }, { DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
{ F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped }, { ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
{ ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0, { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0,
"SGE IQID > 1023 received CPL for FL", -1, 0 }, "SGE IQID > 1023 received CPL for FL", -1, 0 },
{ ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
@ -1520,7 +1520,7 @@ void t4_intr_enable(struct adapter *adapter)
ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 | ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 |
ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO | ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO |
ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR | ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR |
F_DBFIFO_HP_INT | F_DBFIFO_LP_INT | DBFIFO_HP_INT | DBFIFO_LP_INT |
EGRESS_SIZE_ERR); EGRESS_SIZE_ERR);
t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK); t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK);
t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf); t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf);
@ -2033,8 +2033,8 @@ int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len)
if ((addr & 3) || (len + off) > MEMWIN0_APERTURE) if ((addr & 3) || (len + off) > MEMWIN0_APERTURE)
return -EINVAL; return -EINVAL;
t4_write_reg(adap, A_PCIE_MEM_ACCESS_OFFSET, addr & ~15); t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET, addr & ~15);
t4_read_reg(adap, A_PCIE_MEM_ACCESS_OFFSET); t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
for (i = 0; i < len; i += 4) for (i = 0; i < len; i += 4)
*data++ = t4_read_reg(adap, (MEMWIN0_BASE + off + i)); *data++ = t4_read_reg(adap, (MEMWIN0_BASE + off + i));

54
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
View file

@ -190,59 +190,31 @@
#define SGE_DEBUG_DATA_LOW 0x10d4 #define SGE_DEBUG_DATA_LOW 0x10d4
#define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
#define S_LP_INT_THRESH 12
#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
#define S_HP_INT_THRESH 28 #define S_HP_INT_THRESH 28
#define M_HP_INT_THRESH 0xfU
#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
#define M_HP_COUNT 0x7ffU
#define S_HP_COUNT 16
#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
#define S_LP_INT_THRESH 12
#define M_LP_INT_THRESH 0xfU
#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
#define M_LP_COUNT 0x7ffU
#define S_LP_COUNT 0
#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
#define A_SGE_DBFIFO_STATUS 0x10a4 #define A_SGE_DBFIFO_STATUS 0x10a4
#define S_ENABLE_DROP 13 #define S_ENABLE_DROP 13
#define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP) #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
#define F_ENABLE_DROP V_ENABLE_DROP(1U) #define F_ENABLE_DROP V_ENABLE_DROP(1U)
#define S_DROPPED_DB 0
#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
#define F_DROPPED_DB V_DROPPED_DB(1U)
#define A_SGE_DOORBELL_CONTROL 0x10a8 #define A_SGE_DOORBELL_CONTROL 0x10a8
#define A_SGE_CTXT_CMD 0x11fc #define A_SGE_CTXT_CMD 0x11fc
#define A_SGE_DBQ_CTXT_BADDR 0x1084 #define A_SGE_DBQ_CTXT_BADDR 0x1084
#define A_SGE_PF_KDOORBELL 0x0
#define S_QID 15
#define V_QID(x) ((x) << S_QID)
#define S_PIDX 0
#define V_PIDX(x) ((x) << S_PIDX)
#define M_LP_COUNT 0x7ffU
#define S_LP_COUNT 0
#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
#define M_HP_COUNT 0x7ffU
#define S_HP_COUNT 16
#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
#define A_SGE_INT_ENABLE3 0x1040
#define S_DBFIFO_HP_INT 8
#define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
#define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U)
#define S_DBFIFO_LP_INT 7
#define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
#define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U)
#define S_DROPPED_DB 0
#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
#define F_DROPPED_DB V_DROPPED_DB(1U)
#define S_ERR_DROPPED_DB 18
#define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
#define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U)
#define A_PCIE_MEM_ACCESS_OFFSET 0x306c
#define M_HP_INT_THRESH 0xfU
#define M_LP_INT_THRESH 0xfU
#define PCIE_PF_CLI 0x44 #define PCIE_PF_CLI 0x44
#define PCIE_INT_CAUSE 0x3004 #define PCIE_INT_CAUSE 0x3004
#define UNXSPLCPLERR 0x20000000U #define UNXSPLCPLERR 0x20000000U