diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt index d05c3b8713c1..d387336a2b5d 100644 --- a/Documentation/devicetree/bindings/arm/msm/msm.txt +++ b/Documentation/devicetree/bindings/arm/msm/msm.txt @@ -86,6 +86,9 @@ SoCs: - MSMHAMSTER compatible = "qcom,msmhamster" +- MSMFALCON + compatible = "qcom,msmfalcon" + - MSM8952 compatible = "qcom,msm8952" @@ -245,6 +248,7 @@ compatible = "qcom,msmcobalt-rumi" compatible = "qcom,msmhamster-rumi" compatible = "qcom,msmhamster-cdp" compatible = "qcom,msmhamster-mtp" +compatible = "qcom,msmfalcon-sim" compatible = "qcom,msm8952-rumi" compatible = "qcom,msm8952-sim" compatible = "qcom,msm8952-qrd" diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msmfalcon-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msmfalcon-pinctrl.txt new file mode 100644 index 000000000000..929ba3ee688b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msmfalcon-pinctrl.txt @@ -0,0 +1,199 @@ +Qualcomm Technologies, Inc. MSMFALCON TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +MSMFALCON platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,msmfalcon-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio149, + sdc1_clk, + sdc1_cmd, + sdc1_data + sdc2_clk, + sdc2_cmd, + sdc2_data + sdc1_rclk, + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@01010000 { + compatible = "qcom,msmfalcon-pinctrl"; + reg = <0x01010000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart8"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 3a375f5f1911..faf39d2a8970 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -113,6 +113,8 @@ dtb-$(CONFIG_ARCH_MSMCOBALT) += msmcobalt-sim.dtb \ dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb +dtb-$(CONFIG_ARCH_MSMFALCON) += msmfalcon-sim.dtb + always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi new file mode 100644 index 000000000000..a397310d4a61 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi @@ -0,0 +1,36 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@03400000 { + compatible = "qcom,msmfalcon-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart_console_active { + mux { + pins = "gpio0", "gpio1"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts b/arch/arm/boot/dts/qcom/msmfalcon-sim.dts new file mode 100644 index 000000000000..9840343fc3a7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmfalcon-sim.dts @@ -0,0 +1,29 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "msmfalcon.dtsi" +#include "msmfalcon-pinctrl.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM FALCON SIM"; + compatible = "qcom,msmfalcon-sim", "qcom,msmfalcon", "qcom,sim"; + qcom,board-id = <16 0>; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi new file mode 100644 index 000000000000..6d931c1fbb89 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -0,0 +1,235 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. MSM FALCON"; + compatible = "qcom,msmfalcon"; + qcom,msm-id = <317 0x0>; + interrupt-parent = <&intc>; + + aliases { + serial0 = &uartblsp2dm1; + }; + + chosen { + stdout-path = "serial0"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17b00000 0x100000>; /* GICR * 8 */ + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = <1 9 4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + uartblsp2dm1: serial@0c1b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc1b0000 0x1000>; + interrupts = <0 114 0>; + status = "disabled"; + clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + clock-names = "core", "iface"; + }; + + timer@17920000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17920000 0x1000>; + clock-frequency = <19200000>; + + frame@17921000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0x17921000 0x1000>, + <0x17922000 0x1000>; + }; + + frame@17923000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0x17923000 0x1000>; + status = "disabled"; + }; + + frame@17924000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0x17924000 0x1000>; + status = "disabled"; + }; + + frame@17925000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0x17925000 0x1000>; + status = "disabled"; + }; + + frame@17926000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0x17926000 0x1000>; + status = "disabled"; + }; + + frame@17927000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0x17927000 0x1000>; + status = "disabled"; + }; + + frame@17928000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0x17928000 0x1000>; + status = "disabled"; + }; + }; + + clock_gcc: qcom,dummycc { + compatible = "qcom,dummycc"; + #clock-cells = <1>; + }; +}; diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index f04c77bf1269..4e38de7ddd3e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -81,6 +81,14 @@ config ARCH_MSMHAMSTER If you do not wish to build a kernel that runs on this chipset,say 'N' here. +config ARCH_MSMFALCON + bool "Enable Support for Qualcomm Technologies Inc MSMFALCON" + depends on ARCH_QCOM + help + This enables support for the MSMFALCON chipset. + If you do not wish to build a kernel that runs + on this chipset,say 'N' here. + config ARCH_ROCKCHIP bool "Rockchip Platforms" select ARCH_HAS_RESET_CONTROLLER diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index f6b46abb1593..b9819b929a91 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -112,4 +112,12 @@ config PINCTRL_MSM8996 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm MSM8996 platform. +config PINCTRL_MSMFALCON + tristate "Qualcomm MSMFALCON pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm MSMFALCON platform. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 7a0eaedc2631..0d390906ea00 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o obj-$(CONFIG_PINCTRL_MSMCOBALT) += pinctrl-msmcobalt.o +obj-$(CONFIG_PINCTRL_MSMFALCON) += pinctrl-msmfalcon.o diff --git a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c b/drivers/pinctrl/qcom/pinctrl-msmfalcon.c new file mode 100644 index 000000000000..14abb75fffe0 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msmfalcon.c @@ -0,0 +1,1564 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define SOUTH 0x00500000 +#define WEST 0x00100000 +#define EAST 0x00900000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = base + REG_SIZE * id, \ + .io_reg = base + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ + .intr_status_reg = base + 0xc + REG_SIZE * id, \ + .intr_target_reg = base + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc msmfalcon_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "SDC2_CLK"), + PINCTRL_PIN(112, "SDC2_CMD"), + PINCTRL_PIN(113, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); + +static const unsigned int sdc2_clk_pins[] = { 111 }; +static const unsigned int sdc2_cmd_pins[] = { 112 }; +static const unsigned int sdc2_data_pins[] = { 113 }; + +enum msmfalcon_functions { + msm_mux_blsp_spi1, + msm_mux_gpio, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_blsp_uart1, + msm_mux_blsp_spi3, + msm_mux_wlan1_adc1, + msm_mux_atest_usb13, + msm_mux_bimc_dte1, + msm_mux_wlan1_adc0, + msm_mux_atest_usb12, + msm_mux_bimc_dte0, + msm_mux_blsp_i2c1, + msm_mux_blsp_uim1, + msm_mux_ddr_bist, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_blsp_spi2, + msm_mux_phase_flag3, + msm_mux_phase_flag14, + msm_mux_blsp_i2c2, + msm_mux_blsp_uim2, + msm_mux_phase_flag31, + msm_mux_blsp_i2c3, + msm_mux_atest_gpsadc1, + msm_mux_wlan2_adc1, + msm_mux_atest_usb11, + msm_mux_dbg_out, + msm_mux_atest_gpsadc0, + msm_mux_wlan2_adc0, + msm_mux_atest_usb10, + msm_mux_blsp_spi4, + msm_mux_pri_mi2s, + msm_mux_phase_flag26, + msm_mux_qdss_gpio4, + msm_mux_pri_mi2s_ws, + msm_mux_phase_flag27, + msm_mux_qdss_gpio5, + msm_mux_blsp_i2c4, + msm_mux_phase_flag28, + msm_mux_blsp_uart5, + msm_mux_blsp_spi5, + msm_mux_phase_flag5, + msm_mux_blsp_i2c5, + msm_mux_blsp_uim5, + msm_mux_blsp_spi6, + msm_mux_blsp_uart2, + msm_mux_qdss_cti, + msm_mux_sec_mi2s, + msm_mux_sndwire_clk, + msm_mux_phase_flag17, + msm_mux_vsense_clkout, + msm_mux_sndwire_data, + msm_mux_phase_flag18, + msm_mux_blsp_i2c7, + msm_mux_wsa_en1, + msm_mux_phase_flag19, + msm_mux_phase_flag11, + msm_mux_vsense_data0, + msm_mux_blsp_i2c6, + msm_mux_blsp_uim6, + msm_mux_phase_flag12, + msm_mux_vsense_data1, + msm_mux_phase_flag13, + msm_mux_vsense_mode, + msm_mux_blsp_spi7, + msm_mux_BLSP_UART, + msm_mux_vfr_1, + msm_mux_wsa_en2, + msm_mux_phase_flag20, + msm_mux_blsp_spi, + msm_mux_m_voc, + msm_mux_phase_flag21, + msm_mux_phase_flag22, + msm_mux_BLSP_I2C, + msm_mux_phase_flag23, + msm_mux_pwr_modem, + msm_mux_phase_flag24, + msm_mux_qdss_gpio, + msm_mux_cam_mclk, + msm_mux_pwr_nav, + msm_mux_qdss_gpio0, + msm_mux_qspi_data0, + msm_mux_pwr_crypto, + msm_mux_qdss_gpio1, + msm_mux_qspi_data1, + msm_mux_agera_pll, + msm_mux_qdss_gpio2, + msm_mux_qspi_data2, + msm_mux_jitter_bist, + msm_mux_qdss_gpio3, + msm_mux_cci_i2c, + msm_mux_pll_bypassnl, + msm_mux_atest_tsens, + msm_mux_pll_reset, + msm_mux_qdss_gpio9, + msm_mux_CAM_IRQ, + msm_mux_CCI_TIMER3, + msm_mux_CCI_ASYNC, + msm_mux_qspi_cs, + msm_mux_qdss_gpio10, + msm_mux_CAM4_STANDBY, + msm_mux_CCI_TIMER4, + msm_mux_qdss_gpio11, + msm_mux_bt_reset, + msm_mux_cci_async, + msm_mux_qdss_gpio12, + msm_mux_CAM1_RST, + msm_mux_qdss_gpio6, + msm_mux_qdss_gpio7, + msm_mux_FL_FRONT, + msm_mux_CCI_TIMER0, + msm_mux_qdss_gpio8, + msm_mux_FL_STROBE, + msm_mux_CCI_TIMER1, + msm_mux_LASER_CE, + msm_mux_mdss_vsync0, + msm_mux_mdss_vsync1, + msm_mux_mdss_vsync2, + msm_mux_mdss_vsync3, + msm_mux_qdss_gpio13, + msm_mux_CAM2_RST, + msm_mux_qspi_clk, + msm_mux_phase_flag30, + msm_mux_qdss_gpio14, + msm_mux_CAM3_RST, + msm_mux_qspi_resetn, + msm_mux_phase_flag1, + msm_mux_qdss_gpio15, + msm_mux_CAM1_STANDBY, + msm_mux_phase_flag2, + msm_mux_CAM2_STANDBY, + msm_mux_phase_flag9, + msm_mux_CAM3_STANDBY, + msm_mux_qspi_data3, + msm_mux_phase_flag15, + msm_mux_CAM4_RST, + msm_mux_CCI_TIMER2, + msm_mux_phase_flag16, + msm_mux_phase_flag6, + msm_mux_RCM_MARKER2, + msm_mux_phase_flag29, + msm_mux_SS_SWITCH, + msm_mux_phase_flag25, + msm_mux_phase_flag10, + msm_mux_gcc_gp1, + msm_mux_phase_flag4, + msm_mux_USB_DIR, + msm_mux_USB_PHY, + msm_mux_gcc_gp2, + msm_mux_atest_char, + msm_mux_mdp_vsync, + msm_mux_gcc_gp3, + msm_mux_atest_char3, + msm_mux_Lcd_mode, + msm_mux_EDP_HOT, + msm_mux_cri_trng0, + msm_mux_atest_char2, + msm_mux_cri_trng1, + msm_mux_atest_char1, + msm_mux_audio_ref, + msm_mux_MDP_VSYNC, + msm_mux_cri_trng, + msm_mux_atest_char0, + msm_mux_US_EURO, + msm_mux_KEY_FOCUS, + msm_mux_NAV_PPS, + msm_mux_blsp_spi8, + msm_mux_sp_cmu, + msm_mux_SLT_PWR, + msm_mux_adsp_ext, + msm_mux_TS_RESET, + msm_mux_TS_INT, + msm_mux_ssc_irq, + msm_mux_isense_dbg, + msm_mux_phase_flag0, + msm_mux_phase_flag7, + msm_mux_phase_flag8, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_HAPTICS_PWM, + msm_mux_wmss_reset, + msm_mux_mss_lte, + msm_mux_uim2_data, + msm_mux_uim2_clk, + msm_mux_uim2_reset, + msm_mux_uim2_present, + msm_mux_uim1_data, + msm_mux_uim1_clk, + msm_mux_uim1_reset, + msm_mux_uim1_present, + msm_mux_uim_batt, + msm_mux_pa_indicator, + msm_mux_ssbi_gnss, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_qlink_request, + msm_mux_qlink_enable, + msm_mux_prng_rosc, + msm_mux_NA, +}; + +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio46", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio53", "gpio57", "gpio59", + "gpio61", "gpio62", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", +}; +static const char * const tgu_ch0_groups[] = { + "gpio0", +}; +static const char * const tgu_ch1_groups[] = { + "gpio1", +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio30", "gpio65", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio8", +}; +static const char * const atest_usb13_groups[] = { + "gpio8", +}; +static const char * const bimc_dte1_groups[] = { + "gpio8", "gpio10", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio9", +}; +static const char * const atest_usb12_groups[] = { + "gpio9", +}; +static const char * const bimc_dte0_groups[] = { + "gpio9", "gpio11", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; +static const char * const blsp_uim1_groups[] = { + "gpio2", "gpio3", +}; +static const char * const ddr_bist_groups[] = { + "gpio3", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio3", +}; +static const char * const atest_usb1_groups[] = { + "gpio3", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const phase_flag3_groups[] = { + "gpio4", +}; +static const char * const phase_flag14_groups[] = { + "gpio5", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", +}; +static const char * const blsp_uim2_groups[] = { + "gpio6", "gpio7", +}; +static const char * const phase_flag31_groups[] = { + "gpio6", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; +static const char * const atest_gpsadc1_groups[] = { + "gpio10", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const dbg_out_groups[] = { + "gpio11", +}; +static const char * const atest_gpsadc0_groups[] = { + "gpio11", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const pri_mi2s_groups[] = { + "gpio12", "gpio14", "gpio15", "gpio61", +}; +static const char * const phase_flag26_groups[] = { + "gpio12", +}; +static const char * const qdss_gpio4_groups[] = { + "gpio12", "gpio36", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio13", +}; +static const char * const phase_flag27_groups[] = { + "gpio13", +}; +static const char * const qdss_gpio5_groups[] = { + "gpio13", "gpio37", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio14", "gpio15", +}; +static const char * const phase_flag28_groups[] = { + "gpio14", +}; +static const char * const blsp_uart5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const phase_flag5_groups[] = { + "gpio17", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio18", "gpio19", +}; +static const char * const blsp_uim5_groups[] = { + "gpio18", "gpio19", +}; +static const char * const blsp_spi6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const blsp_uart2_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const qdss_cti_groups[] = { + "gpio20", "gpio21", "gpio24", "gpio25", "gpio26", "gpio49", "gpio50", + "gpio61", +}; +static const char * const sec_mi2s_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", "gpio62", +}; +static const char * const sndwire_clk_groups[] = { + "gpio24", +}; +static const char * const phase_flag17_groups[] = { + "gpio24", +}; +static const char * const vsense_clkout_groups[] = { + "gpio24", +}; +static const char * const sndwire_data_groups[] = { + "gpio25", +}; +static const char * const phase_flag18_groups[] = { + "gpio25", +}; +static const char * const blsp_i2c7_groups[] = { + "gpio26", "gpio27", +}; +static const char * const wsa_en1_groups[] = { + "gpio26", +}; +static const char * const phase_flag19_groups[] = { + "gpio26", +}; +static const char * const phase_flag11_groups[] = { + "gpio21", +}; +static const char * const vsense_data0_groups[] = { + "gpio21", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio22", "gpio23", +}; +static const char * const blsp_uim6_groups[] = { + "gpio22", "gpio23", +}; +static const char * const phase_flag12_groups[] = { + "gpio22", +}; +static const char * const vsense_data1_groups[] = { + "gpio22", +}; +static const char * const phase_flag13_groups[] = { + "gpio23", +}; +static const char * const vsense_mode_groups[] = { + "gpio23", +}; +static const char * const blsp_spi7_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const BLSP_UART_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", + "gpio31", +}; +static const char * const vfr_1_groups[] = { + "gpio27", +}; +static const char * const wsa_en2_groups[] = { + "gpio27", +}; +static const char * const phase_flag20_groups[] = { + "gpio27", +}; +static const char * const blsp_spi_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", "gpio40", "gpio41", "gpio44", + "gpio52", +}; +static const char * const m_voc_groups[] = { + "gpio28", +}; +static const char * const phase_flag21_groups[] = { + "gpio28", +}; +static const char * const phase_flag22_groups[] = { + "gpio29", +}; +static const char * const BLSP_I2C_groups[] = { + "gpio30", "gpio31", "gpio44", "gpio52", +}; +static const char * const phase_flag23_groups[] = { + "gpio30", +}; +static const char * const pwr_modem_groups[] = { + "gpio31", +}; +static const char * const phase_flag24_groups[] = { + "gpio31", +}; +static const char * const qdss_gpio_groups[] = { + "gpio31", "gpio41", "gpio68", "gpio69", +}; +static const char * const cam_mclk_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; +static const char * const pwr_nav_groups[] = { + "gpio32", +}; +static const char * const qdss_gpio0_groups[] = { + "gpio32", "gpio62", +}; +static const char * const qspi_data0_groups[] = { + "gpio33", +}; +static const char * const pwr_crypto_groups[] = { + "gpio33", +}; +static const char * const qdss_gpio1_groups[] = { + "gpio33", "gpio63", +}; +static const char * const qspi_data1_groups[] = { + "gpio34", +}; +static const char * const agera_pll_groups[] = { + "gpio34", "gpio36", +}; +static const char * const qdss_gpio2_groups[] = { + "gpio34", "gpio64", +}; +static const char * const qspi_data2_groups[] = { + "gpio35", +}; +static const char * const jitter_bist_groups[] = { + "gpio35", +}; +static const char * const qdss_gpio3_groups[] = { + "gpio35", "gpio65", +}; +static const char * const cci_i2c_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio36", +}; +static const char * const atest_tsens_groups[] = { + "gpio36", +}; +static const char * const pll_reset_groups[] = { + "gpio37", +}; +static const char * const qdss_gpio9_groups[] = { + "gpio42", "gpio76", +}; +static const char * const CAM_IRQ_groups[] = { + "gpio43", +}; +static const char * const CCI_TIMER3_groups[] = { + "gpio43", +}; +static const char * const CCI_ASYNC_groups[] = { + "gpio43", "gpio44", +}; +static const char * const qspi_cs_groups[] = { + "gpio43", "gpio50", +}; +static const char * const qdss_gpio10_groups[] = { + "gpio43", "gpio77", +}; +static const char * const CAM4_STANDBY_groups[] = { + "gpio44", +}; +static const char * const CCI_TIMER4_groups[] = { + "gpio44", +}; +static const char * const qdss_gpio11_groups[] = { + "gpio44", "gpio79", +}; +static const char * const bt_reset_groups[] = { + "gpio45", +}; +static const char * const cci_async_groups[] = { + "gpio45", +}; +static const char * const qdss_gpio12_groups[] = { + "gpio45", "gpio80", +}; +static const char * const CAM1_RST_groups[] = { + "gpio46", +}; +static const char * const qdss_gpio6_groups[] = { + "gpio38", "gpio70", +}; +static const char * const qdss_gpio7_groups[] = { + "gpio39", "gpio71", +}; +static const char * const FL_FRONT_groups[] = { + "gpio40", +}; +static const char * const CCI_TIMER0_groups[] = { + "gpio40", +}; +static const char * const qdss_gpio8_groups[] = { + "gpio40", "gpio75", +}; +static const char * const FL_STROBE_groups[] = { + "gpio41", +}; +static const char * const CCI_TIMER1_groups[] = { + "gpio41", +}; +static const char * const LASER_CE_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync0_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync1_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync2_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync3_groups[] = { + "gpio42", +}; +static const char * const qdss_gpio13_groups[] = { + "gpio46", "gpio78", +}; +static const char * const CAM2_RST_groups[] = { + "gpio47", +}; +static const char * const qspi_clk_groups[] = { + "gpio47", +}; +static const char * const phase_flag30_groups[] = { + "gpio47", +}; +static const char * const qdss_gpio14_groups[] = { + "gpio47", "gpio72", +}; +static const char * const CAM3_RST_groups[] = { + "gpio48", +}; +static const char * const qspi_resetn_groups[] = { + "gpio48", +}; +static const char * const phase_flag1_groups[] = { + "gpio48", +}; +static const char * const qdss_gpio15_groups[] = { + "gpio48", "gpio73", +}; +static const char * const CAM1_STANDBY_groups[] = { + "gpio49", +}; +static const char * const phase_flag2_groups[] = { + "gpio49", +}; +static const char * const CAM2_STANDBY_groups[] = { + "gpio50", +}; +static const char * const phase_flag9_groups[] = { + "gpio50", +}; +static const char * const CAM3_STANDBY_groups[] = { + "gpio51", +}; +static const char * const qspi_data3_groups[] = { + "gpio51", +}; +static const char * const phase_flag15_groups[] = { + "gpio51", +}; +static const char * const CAM4_RST_groups[] = { + "gpio52", +}; +static const char * const CCI_TIMER2_groups[] = { + "gpio52", +}; +static const char * const phase_flag16_groups[] = { + "gpio52", +}; +static const char * const phase_flag6_groups[] = { + "gpio53", +}; +static const char * const RCM_MARKER2_groups[] = { + "gpio54", +}; +static const char * const phase_flag29_groups[] = { + "gpio54", +}; +static const char * const SS_SWITCH_groups[] = { + "gpio55", "gpio56", +}; +static const char * const phase_flag25_groups[] = { + "gpio55", +}; +static const char * const phase_flag10_groups[] = { + "gpio56", +}; +static const char * const gcc_gp1_groups[] = { + "gpio57", "gpio78", +}; +static const char * const phase_flag4_groups[] = { + "gpio57", +}; +static const char * const USB_DIR_groups[] = { + "gpio58", +}; +static const char * const USB_PHY_groups[] = { + "gpio58", +}; +static const char * const gcc_gp2_groups[] = { + "gpio58", "gpio81", +}; +static const char * const atest_char_groups[] = { + "gpio58", +}; +static const char * const mdp_vsync_groups[] = { + "gpio59", "gpio74", +}; +static const char * const gcc_gp3_groups[] = { + "gpio59", "gpio82", +}; +static const char * const atest_char3_groups[] = { + "gpio59", +}; +static const char * const Lcd_mode_groups[] = { + "gpio60", +}; +static const char * const EDP_HOT_groups[] = { + "gpio60", +}; +static const char * const cri_trng0_groups[] = { + "gpio60", +}; +static const char * const atest_char2_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const atest_char1_groups[] = { + "gpio61", +}; +static const char * const audio_ref_groups[] = { + "gpio62", +}; +static const char * const MDP_VSYNC_groups[] = { + "gpio62", +}; +static const char * const cri_trng_groups[] = { + "gpio62", +}; +static const char * const atest_char0_groups[] = { + "gpio62", +}; +static const char * const US_EURO_groups[] = { + "gpio63", +}; +static const char * const KEY_FOCUS_groups[] = { + "gpio64", +}; +static const char * const NAV_PPS_groups[] = { + "gpio64", "gpio65", "gpio98", "gpio98", +}; +static const char * const blsp_spi8_groups[] = { + "gpio64", "gpio76", +}; +static const char * const sp_cmu_groups[] = { + "gpio64", +}; +static const char * const SLT_PWR_groups[] = { + "gpio65", +}; +static const char * const adsp_ext_groups[] = { + "gpio65", +}; +static const char * const TS_RESET_groups[] = { + "gpio66", +}; +static const char * const TS_INT_groups[] = { + "gpio67", +}; +static const char * const ssc_irq_groups[] = { + "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", + "gpio75", "gpio76", "gpio77", +}; +static const char * const isense_dbg_groups[] = { + "gpio68", +}; +static const char * const phase_flag0_groups[] = { + "gpio68", +}; +static const char * const phase_flag7_groups[] = { + "gpio69", +}; +static const char * const phase_flag8_groups[] = { + "gpio70", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio71", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio71", +}; +static const char * const HAPTICS_PWM_groups[] = { + "gpio78", +}; +static const char * const wmss_reset_groups[] = { + "gpio79", +}; +static const char * const mss_lte_groups[] = { + "gpio81", "gpio82", +}; +static const char * const uim2_data_groups[] = { + "gpio83", +}; +static const char * const uim2_clk_groups[] = { + "gpio84", +}; +static const char * const uim2_reset_groups[] = { + "gpio85", +}; +static const char * const uim2_present_groups[] = { + "gpio86", +}; +static const char * const uim1_data_groups[] = { + "gpio87", +}; +static const char * const uim1_clk_groups[] = { + "gpio88", +}; +static const char * const uim1_reset_groups[] = { + "gpio89", +}; +static const char * const uim1_present_groups[] = { + "gpio90", +}; +static const char * const uim_batt_groups[] = { + "gpio91", +}; +static const char * const pa_indicator_groups[] = { + "gpio92", +}; +static const char * const ssbi_gnss_groups[] = { + "gpio94", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const qlink_request_groups[] = { + "gpio99", +}; +static const char * const qlink_enable_groups[] = { + "gpio100", +}; +static const char * const prng_rosc_groups[] = { + "gpio102", +}; + +static const struct msm_function msmfalcon_functions[] = { + FUNCTION(blsp_spi1), + FUNCTION(gpio), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(blsp_uart1), + FUNCTION(blsp_spi3), + FUNCTION(wlan1_adc1), + FUNCTION(atest_usb13), + FUNCTION(bimc_dte1), + FUNCTION(wlan1_adc0), + FUNCTION(atest_usb12), + FUNCTION(bimc_dte0), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_uim1), + FUNCTION(ddr_bist), + FUNCTION(atest_tsens2), + FUNCTION(atest_usb1), + FUNCTION(blsp_spi2), + FUNCTION(phase_flag3), + FUNCTION(phase_flag14), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_uim2), + FUNCTION(phase_flag31), + FUNCTION(blsp_i2c3), + FUNCTION(atest_gpsadc1), + FUNCTION(wlan2_adc1), + FUNCTION(atest_usb11), + FUNCTION(dbg_out), + FUNCTION(atest_gpsadc0), + FUNCTION(wlan2_adc0), + FUNCTION(atest_usb10), + FUNCTION(blsp_spi4), + FUNCTION(pri_mi2s), + FUNCTION(phase_flag26), + FUNCTION(qdss_gpio4), + FUNCTION(pri_mi2s_ws), + FUNCTION(phase_flag27), + FUNCTION(qdss_gpio5), + FUNCTION(blsp_i2c4), + FUNCTION(phase_flag28), + FUNCTION(blsp_uart5), + FUNCTION(blsp_spi5), + FUNCTION(phase_flag5), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_uim5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_uart2), + FUNCTION(qdss_cti), + FUNCTION(sec_mi2s), + FUNCTION(sndwire_clk), + FUNCTION(phase_flag17), + FUNCTION(vsense_clkout), + FUNCTION(sndwire_data), + FUNCTION(phase_flag18), + FUNCTION(blsp_i2c7), + FUNCTION(wsa_en1), + FUNCTION(phase_flag19), + FUNCTION(phase_flag11), + FUNCTION(vsense_data0), + FUNCTION(blsp_i2c6), + FUNCTION(blsp_uim6), + FUNCTION(phase_flag12), + FUNCTION(vsense_data1), + FUNCTION(phase_flag13), + FUNCTION(vsense_mode), + FUNCTION(blsp_spi7), + FUNCTION(BLSP_UART), + FUNCTION(vfr_1), + FUNCTION(wsa_en2), + FUNCTION(phase_flag20), + FUNCTION(blsp_spi), + FUNCTION(m_voc), + FUNCTION(phase_flag21), + FUNCTION(phase_flag22), + FUNCTION(BLSP_I2C), + FUNCTION(phase_flag23), + FUNCTION(pwr_modem), + FUNCTION(phase_flag24), + FUNCTION(qdss_gpio), + FUNCTION(cam_mclk), + FUNCTION(pwr_nav), + FUNCTION(qdss_gpio0), + FUNCTION(qspi_data0), + FUNCTION(pwr_crypto), + FUNCTION(qdss_gpio1), + FUNCTION(qspi_data1), + FUNCTION(agera_pll), + FUNCTION(qdss_gpio2), + FUNCTION(qspi_data2), + FUNCTION(jitter_bist), + FUNCTION(qdss_gpio3), + FUNCTION(cci_i2c), + FUNCTION(pll_bypassnl), + FUNCTION(atest_tsens), + FUNCTION(pll_reset), + FUNCTION(qdss_gpio9), + FUNCTION(CAM_IRQ), + FUNCTION(CCI_TIMER3), + FUNCTION(CCI_ASYNC), + FUNCTION(qspi_cs), + FUNCTION(qdss_gpio10), + FUNCTION(CAM4_STANDBY), + FUNCTION(CCI_TIMER4), + FUNCTION(qdss_gpio11), + FUNCTION(bt_reset), + FUNCTION(cci_async), + FUNCTION(qdss_gpio12), + FUNCTION(CAM1_RST), + FUNCTION(qdss_gpio6), + FUNCTION(qdss_gpio7), + FUNCTION(FL_FRONT), + FUNCTION(CCI_TIMER0), + FUNCTION(qdss_gpio8), + FUNCTION(FL_STROBE), + FUNCTION(CCI_TIMER1), + FUNCTION(LASER_CE), + FUNCTION(mdss_vsync0), + FUNCTION(mdss_vsync1), + FUNCTION(mdss_vsync2), + FUNCTION(mdss_vsync3), + FUNCTION(qdss_gpio13), + FUNCTION(CAM2_RST), + FUNCTION(qspi_clk), + FUNCTION(phase_flag30), + FUNCTION(qdss_gpio14), + FUNCTION(CAM3_RST), + FUNCTION(qspi_resetn), + FUNCTION(phase_flag1), + FUNCTION(qdss_gpio15), + FUNCTION(CAM1_STANDBY), + FUNCTION(phase_flag2), + FUNCTION(CAM2_STANDBY), + FUNCTION(phase_flag9), + FUNCTION(CAM3_STANDBY), + FUNCTION(qspi_data3), + FUNCTION(phase_flag15), + FUNCTION(CAM4_RST), + FUNCTION(CCI_TIMER2), + FUNCTION(phase_flag16), + FUNCTION(phase_flag6), + FUNCTION(RCM_MARKER2), + FUNCTION(phase_flag29), + FUNCTION(SS_SWITCH), + FUNCTION(phase_flag25), + FUNCTION(phase_flag10), + FUNCTION(gcc_gp1), + FUNCTION(phase_flag4), + FUNCTION(USB_DIR), + FUNCTION(USB_PHY), + FUNCTION(gcc_gp2), + FUNCTION(atest_char), + FUNCTION(mdp_vsync), + FUNCTION(gcc_gp3), + FUNCTION(atest_char3), + FUNCTION(Lcd_mode), + FUNCTION(EDP_HOT), + FUNCTION(cri_trng0), + FUNCTION(atest_char2), + FUNCTION(cri_trng1), + FUNCTION(atest_char1), + FUNCTION(audio_ref), + FUNCTION(MDP_VSYNC), + FUNCTION(cri_trng), + FUNCTION(atest_char0), + FUNCTION(US_EURO), + FUNCTION(KEY_FOCUS), + FUNCTION(NAV_PPS), + FUNCTION(blsp_spi8), + FUNCTION(sp_cmu), + FUNCTION(SLT_PWR), + FUNCTION(adsp_ext), + FUNCTION(TS_RESET), + FUNCTION(TS_INT), + FUNCTION(ssc_irq), + FUNCTION(isense_dbg), + FUNCTION(phase_flag0), + FUNCTION(phase_flag7), + FUNCTION(phase_flag8), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(HAPTICS_PWM), + FUNCTION(wmss_reset), + FUNCTION(mss_lte), + FUNCTION(uim2_data), + FUNCTION(uim2_clk), + FUNCTION(uim2_reset), + FUNCTION(uim2_present), + FUNCTION(uim1_data), + FUNCTION(uim1_clk), + FUNCTION(uim1_reset), + FUNCTION(uim1_present), + FUNCTION(uim_batt), + FUNCTION(pa_indicator), + FUNCTION(ssbi_gnss), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(qlink_request), + FUNCTION(qlink_enable), + FUNCTION(prng_rosc), +}; + +static const struct msm_pingroup msmfalcon_groups[] = { + PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, tgu_ch0, NA, NA, NA, NA, NA, + NA), + PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, tgu_ch1, NA, NA, NA, NA, NA, + NA), + PINGROUP(2, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, blsp_uim1, NA, NA, + NA, NA, NA), + PINGROUP(3, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, blsp_uim1, + ddr_bist, NA, atest_tsens2, atest_usb1, NA), + PINGROUP(4, WEST, blsp_spi2, phase_flag3, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, WEST, blsp_spi2, phase_flag14, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, WEST, blsp_spi2, blsp_i2c2, blsp_uim2, phase_flag31, NA, + NA, NA, NA, NA), + PINGROUP(7, WEST, blsp_spi2, blsp_i2c2, blsp_uim2, NA, NA, NA, NA, NA, + NA), + PINGROUP(8, WEST, blsp_spi3, ddr_bist, NA, NA, wlan1_adc1, atest_usb13, + bimc_dte1, NA, NA), + PINGROUP(9, WEST, blsp_spi3, ddr_bist, NA, NA, wlan1_adc0, atest_usb12, + bimc_dte0, NA, NA), + PINGROUP(10, WEST, blsp_spi3, blsp_i2c3, ddr_bist, NA, atest_gpsadc1, + wlan2_adc1, atest_usb11, bimc_dte1, NA), + PINGROUP(11, WEST, blsp_spi3, blsp_i2c3, dbg_out, atest_gpsadc0, + wlan2_adc0, atest_usb10, bimc_dte0, NA, NA), + PINGROUP(12, SOUTH, blsp_spi4, pri_mi2s, phase_flag26, qdss_gpio4, NA, + NA, NA, NA, NA), + PINGROUP(13, SOUTH, blsp_spi4, pri_mi2s_ws, NA, phase_flag27, + qdss_gpio5, NA, NA, NA, NA), + PINGROUP(14, SOUTH, blsp_spi4, blsp_i2c4, pri_mi2s, phase_flag28, NA, + NA, NA, NA, NA), + PINGROUP(15, SOUTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, NA, NA, NA, NA, + NA), + PINGROUP(16, WEST, blsp_uart5, blsp_spi5, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, WEST, blsp_uart5, blsp_spi5, phase_flag5, NA, NA, NA, NA, + NA, NA), + PINGROUP(18, WEST, blsp_uart5, blsp_spi5, blsp_i2c5, blsp_uim5, NA, NA, + NA, NA, NA), + PINGROUP(19, WEST, blsp_uart5, blsp_spi5, blsp_i2c5, blsp_uim5, NA, NA, + NA, NA, NA), + PINGROUP(20, WEST, blsp_spi6, blsp_uart2, NA, qdss_cti, NA, NA, NA, NA, + NA), + PINGROUP(21, WEST, blsp_spi6, blsp_uart2, phase_flag11, qdss_cti, + vsense_data0, NA, NA, NA, NA), + PINGROUP(22, WEST, blsp_spi6, blsp_uart2, blsp_i2c6, blsp_uim6, + phase_flag12, vsense_data1, NA, NA, NA), + PINGROUP(23, WEST, blsp_spi6, blsp_uart2, blsp_i2c6, blsp_uim6, + phase_flag13, vsense_mode, NA, NA, NA), + PINGROUP(24, WEST, blsp_spi7, BLSP_UART, sec_mi2s, sndwire_clk, NA, + phase_flag17, qdss_cti, vsense_clkout, NA), + PINGROUP(25, WEST, blsp_spi7, BLSP_UART, sec_mi2s, sndwire_data, NA, + phase_flag18, qdss_cti, NA, NA), + PINGROUP(26, WEST, blsp_spi7, BLSP_UART, blsp_i2c7, sec_mi2s, wsa_en1, + phase_flag19, qdss_cti, NA, NA), + PINGROUP(27, WEST, blsp_spi7, BLSP_UART, blsp_i2c7, vfr_1, sec_mi2s, + wsa_en2, phase_flag20, NA, NA), + PINGROUP(28, SOUTH, blsp_spi, BLSP_UART, m_voc, phase_flag21, NA, NA, + NA, NA, NA), + PINGROUP(29, SOUTH, blsp_spi, BLSP_UART, NA, phase_flag22, NA, NA, NA, + NA, NA), + PINGROUP(30, SOUTH, blsp_spi, BLSP_UART, BLSP_I2C, blsp_spi3, + phase_flag23, NA, NA, NA, NA), + PINGROUP(31, SOUTH, blsp_spi, BLSP_UART, BLSP_I2C, pwr_modem, + phase_flag24, qdss_gpio, NA, NA, NA), + PINGROUP(32, SOUTH, cam_mclk, pwr_nav, NA, qdss_gpio0, NA, NA, NA, NA, + NA), + PINGROUP(33, SOUTH, cam_mclk, qspi_data0, pwr_crypto, NA, qdss_gpio1, + NA, NA, NA, NA), + PINGROUP(34, SOUTH, cam_mclk, qspi_data1, agera_pll, NA, qdss_gpio2, + NA, NA, NA, NA), + PINGROUP(35, SOUTH, cam_mclk, qspi_data2, jitter_bist, NA, qdss_gpio3, + NA, NA, NA, NA), + PINGROUP(36, SOUTH, cci_i2c, pll_bypassnl, agera_pll, NA, qdss_gpio4, + atest_tsens, NA, NA, NA), + PINGROUP(37, SOUTH, cci_i2c, pll_reset, NA, qdss_gpio5, NA, NA, NA, NA, + NA), + PINGROUP(38, SOUTH, cci_i2c, NA, qdss_gpio6, NA, NA, NA, NA, NA, NA), + PINGROUP(39, SOUTH, cci_i2c, NA, qdss_gpio7, NA, NA, NA, NA, NA, NA), + PINGROUP(40, SOUTH, CCI_TIMER0, NA, blsp_spi, NA, qdss_gpio8, NA, NA, + NA, NA), + PINGROUP(41, SOUTH, CCI_TIMER1, NA, blsp_spi, NA, qdss_gpio, NA, NA, + NA, NA), + PINGROUP(42, SOUTH, mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, + NA, qdss_gpio9, NA, NA, NA), + PINGROUP(43, SOUTH, CCI_TIMER3, CCI_ASYNC, qspi_cs, NA, qdss_gpio10, + NA, NA, NA, NA), + PINGROUP(44, SOUTH, CCI_TIMER4, CCI_ASYNC, blsp_spi, BLSP_I2C, NA, + qdss_gpio11, NA, NA, NA), + PINGROUP(45, SOUTH, cci_async, NA, qdss_gpio12, NA, NA, NA, NA, NA, NA), + PINGROUP(46, SOUTH, blsp_spi1, NA, qdss_gpio13, NA, NA, NA, NA, NA, NA), + PINGROUP(47, SOUTH, qspi_clk, phase_flag30, qdss_gpio14, NA, NA, NA, + NA, NA, NA), + PINGROUP(48, SOUTH, qspi_resetn, phase_flag1, qdss_gpio15, NA, NA, NA, + NA, NA, NA), + PINGROUP(49, SOUTH, phase_flag2, qdss_cti, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, SOUTH, qspi_cs, phase_flag9, qdss_cti, NA, NA, NA, NA, NA, + NA), + PINGROUP(51, SOUTH, qspi_data3, phase_flag15, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(52, EAST, CCI_TIMER2, blsp_spi, BLSP_I2C, phase_flag16, NA, + NA, NA, NA, NA), + PINGROUP(53, EAST, phase_flag6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, EAST, NA, phase_flag29, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, WEST, phase_flag25, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, WEST, phase_flag10, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, SOUTH, gcc_gp1, phase_flag4, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, SOUTH, USB_PHY, gcc_gp2, NA, atest_char, NA, NA, NA, NA, + NA), + PINGROUP(59, EAST, mdp_vsync, gcc_gp3, NA, atest_char3, NA, NA, NA, NA, + NA), + PINGROUP(60, EAST, EDP_HOT, cri_trng0, NA, atest_char2, NA, NA, NA, NA, + NA), + PINGROUP(61, EAST, pri_mi2s, cri_trng1, NA, qdss_cti, atest_char1, NA, + NA, NA, NA), + PINGROUP(62, SOUTH, sec_mi2s, audio_ref, MDP_VSYNC, cri_trng, NA, + qdss_gpio0, atest_char0, NA, NA), + PINGROUP(63, SOUTH, NA, NA, qdss_gpio1, NA, NA, NA, NA, NA, NA), + PINGROUP(64, SOUTH, NAV_PPS, blsp_spi8, sp_cmu, NA, qdss_gpio2, NA, NA, + NA, NA), + PINGROUP(65, SOUTH, NAV_PPS, blsp_spi3, NA, adsp_ext, NA, qdss_gpio3, + NA, NA, NA), + PINGROUP(66, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, SOUTH, isense_dbg, phase_flag0, qdss_gpio, NA, NA, NA, NA, + NA, NA), + PINGROUP(69, SOUTH, phase_flag7, qdss_gpio, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, SOUTH, phase_flag8, qdss_gpio6, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(71, SOUTH, NA, qdss_gpio7, tsense_pwm1, tsense_pwm2, NA, NA, + NA, NA, NA), + PINGROUP(72, SOUTH, qdss_gpio14, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, SOUTH, NA, qdss_gpio15, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, SOUTH, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, WEST, NA, qdss_gpio8, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, WEST, blsp_spi8, NA, NA, qdss_gpio9, NA, NA, NA, NA, NA), + PINGROUP(77, SOUTH, NA, qdss_gpio10, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, SOUTH, gcc_gp1, qdss_gpio13, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, SOUTH, NA, qdss_gpio11, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, SOUTH, NA, qdss_gpio12, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, SOUTH, mss_lte, gcc_gp2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, SOUTH, mss_lte, NA, gcc_gp3, NA, NA, NA, NA, NA, NA), + PINGROUP(83, SOUTH, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, SOUTH, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, SOUTH, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, SOUTH, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, SOUTH, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, SOUTH, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, SOUTH, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, SOUTH, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, SOUTH, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, SOUTH, NA, NA, pa_indicator, NA, NA, NA, NA, NA, NA), + PINGROUP(93, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, SOUTH, NA, ssbi_gnss, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, SOUTH, NA, NA, ldo_en, NA, NA, NA, NA, NA, NA), + PINGROUP(98, SOUTH, NA, NAV_PPS, NAV_PPS, ldo_update, NA, NA, NA, NA, + NA), + PINGROUP(99, SOUTH, qlink_request, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, SOUTH, qlink_enable, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, SOUTH, NA, prng_rosc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, EAST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, EAST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, EAST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, EAST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_QDSD_PINGROUP(sdc2_clk, 0x999000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x999000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x999000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data msmfalcon_pinctrl = { + .pins = msmfalcon_pins, + .npins = ARRAY_SIZE(msmfalcon_pins), + .functions = msmfalcon_functions, + .nfunctions = ARRAY_SIZE(msmfalcon_functions), + .groups = msmfalcon_groups, + .ngroups = ARRAY_SIZE(msmfalcon_groups), + .ngpios = 111, +}; + +static int msmfalcon_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msmfalcon_pinctrl); +} + +static const struct of_device_id msmfalcon_pinctrl_of_match[] = { + { .compatible = "qcom,msmfalcon-pinctrl", }, + { }, +}; + +static struct platform_driver msmfalcon_pinctrl_driver = { + .driver = { + .name = "msmfalcon-pinctrl", + .owner = THIS_MODULE, + .of_match_table = msmfalcon_pinctrl_of_match, + }, + .probe = msmfalcon_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msmfalcon_pinctrl_init(void) +{ + return platform_driver_register(&msmfalcon_pinctrl_driver); +} +arch_initcall(msmfalcon_pinctrl_init); + +static void __exit msmfalcon_pinctrl_exit(void) +{ + platform_driver_unregister(&msmfalcon_pinctrl_driver); +} +module_exit(msmfalcon_pinctrl_exit); + +MODULE_DESCRIPTION("QTI msmfalcon pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msmfalcon_pinctrl_of_match); diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index c26e530c61f5..4f29923e054c 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -534,6 +534,9 @@ static struct msm_soc_info cpu_of_id[] = { /* Cobalt ID */ [306] = {MSM_CPU_HAMSTER, "MSMHAMSTER"}, + /* falcon ID */ + [317] = {MSM_CPU_FALCON, "MSMFALCON"}, + /* Uninitialized IDs are not known to run Linux. MSM_CPU_UNKNOWN is set to 0 to ensure these IDs are considered as unknown CPU. */ @@ -1198,6 +1201,10 @@ static void * __init setup_dummy_socinfo(void) dummy_socinfo.id = 306; strlcpy(dummy_socinfo.build_id, "msmhamster - ", sizeof(dummy_socinfo.build_id)); + } else if (early_machine_is_msmfalcon()) { + dummy_socinfo.id = 317; + strlcpy(dummy_socinfo.build_id, "msmfalcon - ", + sizeof(dummy_socinfo.build_id)); } strlcat(dummy_socinfo.build_id, "Dummy socinfo", diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h index a39e42ce4593..39527ed83fa7 100644 --- a/include/soc/qcom/socinfo.h +++ b/include/soc/qcom/socinfo.h @@ -92,6 +92,8 @@ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmcobalt") #define early_machine_is_msmhamster() \ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmhamster") +#define early_machine_is_msmfalcon() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmfalcon") #else #define of_board_is_sim() 0 #define of_board_is_rumi() 0 @@ -127,6 +129,7 @@ #define early_machine_is_msm8929() 0 #define early_machine_is_msmcobalt() 0 #define early_machine_is_msmhamster() 0 +#define early_machine_is_msmfalcon() 0 #endif #define PLATFORM_SUBTYPE_MDM 1 @@ -185,6 +188,7 @@ enum msm_cpu { MSM_CPU_8929, MSM_CPU_COBALT, MSM_CPU_HAMSTER, + MSM_CPU_FALCON, }; struct msm_soc_info {