ARM: Fix ioremap_cached()/ioremap_wc() for SMP platforms
Write combining/cached device mappings are not setting the shared bit, which could potentially cause problems on SMP systems since the cache lines won't participate in the cache coherency protocol. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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@ -420,6 +420,10 @@ static void __init build_mem_type_table(void)
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user_pgprot |= L_PTE_SHARED;
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user_pgprot |= L_PTE_SHARED;
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kern_pgprot |= L_PTE_SHARED;
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kern_pgprot |= L_PTE_SHARED;
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vecs_pgprot |= L_PTE_SHARED;
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vecs_pgprot |= L_PTE_SHARED;
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mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
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mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
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mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
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mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
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mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
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mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
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mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
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mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
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#endif
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#endif
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