evie/android_kernel_oneplus_msm8998
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x86/mce: Create helper function to save addr/misc when needed

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The MCI_STATUS_MISCV and MCI_STATUS_ADDRV bits in the bank status
registers define whether the MISC and ADDR registers respectively
contain valid data - provide a helper function to check these bits
and read the registers when needed.

In addition, processors that support software error recovery (as
indicated by the MCG_SER_P bit in the MCG_CAP register) may include
some undefined bits in the ADDR register - mask these out.

Acked-by: Borislav Petkov <bp@amd64.org>
Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Tony Luck 2011-12-13 09:48:13 -08:00
parent 7329bbeb92
commit 85f92694af
1 changed files with 23 additions and 8 deletions
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31
arch/x86/kernel/cpu/mcheck/mce.c
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@ -492,6 +492,27 @@ static void mce_report_event(struct pt_regs *regs)
irq_work_queue(&__get_cpu_var(mce_irq_work)); irq_work_queue(&__get_cpu_var(mce_irq_work));
} }
/*
* Read ADDR and MISC registers.
*/
static void mce_read_aux(struct mce *m, int i)
{
if (m->status & MCI_STATUS_MISCV)
m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
if (m->status & MCI_STATUS_ADDRV) {
m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
/*
* Mask the reported address by the reported granularity.
*/
if (mce_ser && (m->status & MCI_STATUS_MISCV)) {
u8 shift = MCI_MISC_ADDR_LSB(m->misc);
m->addr >>= shift;
m->addr <<= shift;
}
}
}
DEFINE_PER_CPU(unsigned, mce_poll_count); DEFINE_PER_CPU(unsigned, mce_poll_count);
/* /*
@ -542,10 +563,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
continue; continue;
if (m.status & MCI_STATUS_MISCV) mce_read_aux(&m, i);
m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
if (m.status & MCI_STATUS_ADDRV)
m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
if (!(flags & MCP_TIMESTAMP)) if (!(flags & MCP_TIMESTAMP))
m.tsc = 0; m.tsc = 0;
@ -981,10 +999,7 @@ void do_machine_check(struct pt_regs *regs, long error_code)
if (severity == MCE_AR_SEVERITY) if (severity == MCE_AR_SEVERITY)
kill_it = 1; kill_it = 1;
if (m.status & MCI_STATUS_MISCV) mce_read_aux(&m, i);
m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
if (m.status & MCI_STATUS_ADDRV)
m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
/* /*
* Action optional error. Queue address for later processing. * Action optional error. Queue address for later processing.