MIPS: Alchemy: Fix PCI PM
Move PCI Controller PM to syscore_ops since the platform_driver PM methods are called way too late on resume and far too early on suspend (after and before PCI device resume/suspend). This also allows to simplify wired entry management a bit. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
5611cc4572
commit
864c6c22e9
1 changed files with 67 additions and 70 deletions
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@ -13,6 +13,7 @@
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/syscore_ops.h>
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#include <linux/vmalloc.h>
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#include <linux/vmalloc.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1000.h>
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@ -41,6 +42,12 @@ struct alchemy_pci_context {
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int (*board_pci_idsel)(unsigned int devsel, int assert);
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int (*board_pci_idsel)(unsigned int devsel, int assert);
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};
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};
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/* for syscore_ops. There's only one PCI controller on Alchemy chips, so this
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* should suffice for now.
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*/
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static struct alchemy_pci_context *__alchemy_pci_ctx;
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/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr
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/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr
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* in arch/mips/alchemy/common/setup.c
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* in arch/mips/alchemy/common/setup.c
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*/
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*/
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@ -99,18 +106,6 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
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return -1;
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return -1;
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}
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}
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/* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
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* on resume, clearing our wired entry. Unfortunately the ->resume()
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* callback is called way way way too late (and ->suspend() too early)
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* to have them destroy and recreate it. Instead just test if c0_wired
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* is now lower than the index we retrieved before suspending and then
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* recreate the entry if necessary. Of course this is totally bonkers
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* and breaks as soon as someone else adds another wired entry somewhere
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* else. Anyone have any ideas how to handle this better?
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*/
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if (unlikely(read_c0_wired() < ctx->wired_entry))
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alchemy_pci_wired_entry(ctx);
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local_irq_save(flags);
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local_irq_save(flags);
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r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
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r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
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r |= PCI_STATCMD_STATUS(0x2000);
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r |= PCI_STATCMD_STATUS(0x2000);
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@ -304,6 +299,62 @@ static int alchemy_pci_def_idsel(unsigned int devsel, int assert)
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return 1; /* success */
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return 1; /* success */
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}
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}
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/* save PCI controller register contents. */
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static int alchemy_pci_suspend(void)
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{
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struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
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if (!ctx)
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return 0;
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ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM);
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ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
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ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
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ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
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ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
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ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
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ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
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ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID);
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ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
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ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM);
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ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
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ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
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return 0;
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}
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static void alchemy_pci_resume(void)
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{
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struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
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if (!ctx)
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return;
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__raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM);
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__raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH);
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__raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID);
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__raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID);
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__raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV);
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__raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL);
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__raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID);
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__raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV);
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__raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM);
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__raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
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__raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
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wmb();
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__raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG);
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wmb();
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/* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
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* on resume, making it necessary to recreate it as soon as possible.
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*/
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ctx->wired_entry = 8191; /* impossibly high value */
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alchemy_pci_wired_entry(ctx); /* install it */
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}
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static struct syscore_ops alchemy_pci_pmops = {
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.suspend = alchemy_pci_suspend,
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.resume = alchemy_pci_resume,
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};
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static int __devinit alchemy_pci_probe(struct platform_device *pdev)
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static int __devinit alchemy_pci_probe(struct platform_device *pdev)
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{
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{
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struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
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struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
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@ -396,7 +447,8 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev)
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ret = -ENOMEM;
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ret = -ENOMEM;
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goto out4;
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goto out4;
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}
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}
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ctx->wired_entry = 8192; /* impossibly high value */
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ctx->wired_entry = 8191; /* impossibly high value */
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alchemy_pci_wired_entry(ctx); /* install it */
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set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
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set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
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@ -408,7 +460,9 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev)
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__raw_writel(val, ctx->regs + PCI_REG_CONFIG);
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__raw_writel(val, ctx->regs + PCI_REG_CONFIG);
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wmb();
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wmb();
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__alchemy_pci_ctx = ctx;
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platform_set_drvdata(pdev, ctx);
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platform_set_drvdata(pdev, ctx);
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register_syscore_ops(&alchemy_pci_pmops);
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register_pci_controller(&ctx->alchemy_pci_ctrl);
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register_pci_controller(&ctx->alchemy_pci_ctrl);
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return 0;
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return 0;
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@ -425,68 +479,11 @@ out:
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return ret;
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return ret;
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}
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}
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#ifdef CONFIG_PM
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/* save PCI controller register contents. */
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static int alchemy_pci_suspend(struct device *dev)
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{
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struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
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ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM);
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ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
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ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
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ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
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ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
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ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
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ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
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ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID);
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ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
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ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM);
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ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
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ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
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return 0;
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}
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static int alchemy_pci_resume(struct device *dev)
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{
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struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
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__raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM);
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__raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH);
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__raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID);
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__raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID);
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__raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV);
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__raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL);
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__raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID);
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__raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV);
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__raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM);
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__raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
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__raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
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wmb();
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__raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG);
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wmb();
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return 0;
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}
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static const struct dev_pm_ops alchemy_pci_pmops = {
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.suspend = alchemy_pci_suspend,
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.resume = alchemy_pci_resume,
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};
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#define ALCHEMY_PCICTL_PM (&alchemy_pci_pmops)
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#else
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#define ALCHEMY_PCICTL_PM NULL
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#endif
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static struct platform_driver alchemy_pcictl_driver = {
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static struct platform_driver alchemy_pcictl_driver = {
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.probe = alchemy_pci_probe,
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.probe = alchemy_pci_probe,
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.driver = {
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.driver = {
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.name = "alchemy-pci",
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.name = "alchemy-pci",
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.owner = THIS_MODULE,
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.owner = THIS_MODULE,
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.pm = ALCHEMY_PCICTL_PM,
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},
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},
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};
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};
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