From 1da3212330ae8a1ce12789976c87fe969d9b5eb6 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Fri, 2 Dec 2016 12:31:22 -0800 Subject: [PATCH 1/3] input: qpnp-power-on: Cleanup the qpnp-power-on driver Fix the following in qpnp-power-on driver: - Use GENMASK for bit mask - Remove unused module parameter - Use nested comments properly wherever applicable - Fix conditional block formatting and typos - Use const qualifier for of_device_id table Change-Id: Ib9dd9be6cafad4c7aec1c88d9828ef1ebbe2a1c3 Signed-off-by: Subbaraman Narayanamurthy --- drivers/input/qpnp-power-on.c | 50 +++++++++++++++-------------------- 1 file changed, 21 insertions(+), 29 deletions(-) diff --git a/drivers/input/qpnp-power-on.c b/drivers/input/qpnp-power-on.c index a4057045e3e4..693821d85412 100644 --- a/drivers/input/qpnp-power-on.c +++ b/drivers/input/qpnp-power-on.c @@ -32,11 +32,6 @@ #include #include -#define CREATE_MASK(NUM_BITS, POS) \ - ((unsigned char) (((1 << (NUM_BITS)) - 1) << (POS))) -#define PON_MASK(MSB_BIT, LSB_BIT) \ - CREATE_MASK(MSB_BIT - LSB_BIT + 1, LSB_BIT) - #define PMIC_VER_8941 0x01 #define PMIC_VERSION_REG 0x0105 #define PMIC_VERSION_REV4_REG 0x0103 @@ -135,7 +130,7 @@ #define QPNP_PON_S3_SRC_KPDPWR_AND_RESIN 2 #define QPNP_PON_S3_SRC_KPDPWR_OR_RESIN 3 #define QPNP_PON_S3_SRC_MASK 0x3 -#define QPNP_PON_HARD_RESET_MASK PON_MASK(7, 5) +#define QPNP_PON_HARD_RESET_MASK GENMASK(7, 5) #define QPNP_PON_UVLO_DLOAD_EN BIT(7) #define QPNP_PON_SMPL_EN BIT(7) @@ -227,7 +222,7 @@ static DEFINE_SPINLOCK(spon_list_slock); static LIST_HEAD(spon_dev_list); static u32 s1_delay[PON_S1_COUNT_MAX + 1] = { - 0 , 32, 56, 80, 138, 184, 272, 408, 608, 904, 1352, 2048, + 0, 32, 56, 80, 138, 184, 272, 408, 608, 904, 1352, 2048, 3072, 4480, 6720, 10256 }; @@ -292,14 +287,6 @@ static const char * const qpnp_poff_reason[] = { [39] = "Triggered from S3_RESET_KPDPWR_ANDOR_RESIN (power key and/or reset line)", }; -/* - * On the kernel command line specify - * qpnp-power-on.warm_boot=1 to indicate a warm - * boot of the device. - */ -static int warm_boot; -module_param(warm_boot, int, 0); - static int qpnp_pon_masked_write(struct qpnp_pon *pon, u16 addr, u8 mask, u8 val) { @@ -349,10 +336,10 @@ int qpnp_pon_set_restart_reason(enum pon_restart_reason reason) if (is_pon_gen2(pon)) rc = qpnp_pon_masked_write(pon, QPNP_PON_SOFT_RB_SPARE(pon), - PON_MASK(7, 1), (reason << 1)); + GENMASK(7, 1), (reason << 1)); else rc = qpnp_pon_masked_write(pon, QPNP_PON_SOFT_RB_SPARE(pon), - PON_MASK(7, 2), (reason << 2)); + GENMASK(7, 2), (reason << 2)); if (rc) dev_err(&pon->pdev->dev, @@ -795,7 +782,8 @@ qpnp_pon_input_dispatch(struct qpnp_pon *pon, u32 pon_type) cfg->key_code, pon_rt_sts); key_status = pon_rt_sts & pon_rt_bit; - /* simulate press event in case release event occured + /* + * simulate press event in case release event occurred * without a press event */ if (!cfg->old_state && !key_status) { @@ -1258,7 +1246,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon) if (rc == -EINVAL) { dev_dbg(&pon->pdev->dev, "'qcom,support-reset' DT property doesn't exist\n"); - } else { + } else { dev_err(&pon->pdev->dev, "Unable to read 'qcom,support-reset'\n"); return rc; @@ -1280,10 +1268,12 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon) } } - /* If the value read from REVISION2 register is 0x00, - then there is a single register to control s2 reset. - Otherwise there are separate registers for s2 reset - type and s2 reset enable */ + /* + * If the value read from REVISION2 register is 0x00, + * then there is a single register to control s2 reset. + * Otherwise there are separate registers for s2 reset + * type and s2 reset enable. + */ if (pon->pon_ver == QPNP_PON_GEN1_V1) { cfg->s2_cntl_addr = cfg->s2_cntl2_addr = QPNP_PON_KPDPWR_S2_CNTL(pon); @@ -1344,8 +1334,10 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon) return rc; } - /*PM8941 V3 does not have harware bug. Hence - bark is not required from PMIC versions 3.0*/ + /* + * PM8941 V3 does not have hardware bug. Hence + * bark is not required from PMIC versions 3.0. + */ if (!(revid_rev4 == PMIC8941_V1_REV4 || revid_rev4 == PMIC8941_V2_REV4)) { cfg->support_reset = false; @@ -1669,7 +1661,8 @@ static int pon_regulator_init(struct qpnp_pon *pon) return rc; } - init_data = of_get_regulator_init_data(dev, node, &pon_reg->rdesc); + init_data = of_get_regulator_init_data(dev, node, + &pon_reg->rdesc); if (!init_data) { dev_err(dev, "regulator init data is missing\n"); return -EINVAL; @@ -1847,8 +1840,7 @@ static void qpnp_pon_debugfs_init(struct platform_device *pdev) dev_err(&pon->pdev->dev, "Unable to create debugfs directory\n"); } else { - ent = debugfs_create_file("uvlo_panic", - S_IFREG | S_IWUSR | S_IRUGO, + ent = debugfs_create_file("uvlo_panic", 0644, pon->debugfs, pon, &qpnp_pon_debugfs_uvlo_fops); if (!ent) dev_err(&pon->pdev->dev, @@ -2308,7 +2300,7 @@ static int qpnp_pon_remove(struct platform_device *pdev) return 0; } -static struct of_device_id spmi_match_table[] = { +static const struct of_device_id spmi_match_table[] = { { .compatible = "qcom,qpnp-power-on", }, {} }; From 6fbee0d3f22cc3a839f37b6fa29fcc283b7b18d1 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Fri, 2 Dec 2016 14:15:08 -0800 Subject: [PATCH 2/3] input: qpnp-power-on: Configure debounce delay for PON GEN2 properly Debounce delay range and hence the bit encodings got changed in PON GEN2 peripheral. Fix qpnp_pon_set_dbc() to configure the debounce delay properly. CRs-Fixed: 1097089 Change-Id: Ia3d474a04e11c7d16a1507d65e99001cf844947b Signed-off-by: Subbaraman Narayanamurthy --- .../bindings/input/qpnp-power-on.txt | 13 +++++--- drivers/input/qpnp-power-on.c | 32 ++++++++++++------- 2 files changed, 29 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/input/qpnp-power-on.txt b/Documentation/devicetree/bindings/input/qpnp-power-on.txt index 5b364d0a77ba..a596aa1c595d 100644 --- a/Documentation/devicetree/bindings/input/qpnp-power-on.txt +++ b/Documentation/devicetree/bindings/input/qpnp-power-on.txt @@ -24,11 +24,14 @@ Required properties: Optional properties: - qcom,pon-dbc-delay The debounce delay for the power-key interrupt - specified in us. The value ranges from 2 - seconds to 1/64 of a second. Possible values - are: - - 2, 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 - - Intermediate value is rounded down to the + specified in us. + Possible values for GEN1 PON are: + 15625, 31250, 62500, 125000, 250000, 500000, + 1000000 and 2000000. + Possible values for GEN2 PON are: + 62, 123, 245, 489, 977, 1954, 3907, 7813, + 15625, 31250, 62500, 125000 and 250000. + Intermediate value is rounded down to the nearest valid value. - qcom,pon_1 ...pon_n These represent the child nodes which describe the properties (reset, key) for each of the pon diff --git a/drivers/input/qpnp-power-on.c b/drivers/input/qpnp-power-on.c index 693821d85412..b9fe20c20b55 100644 --- a/drivers/input/qpnp-power-on.c +++ b/drivers/input/qpnp-power-on.c @@ -104,6 +104,7 @@ #define QPNP_PON_S2_CNTL_EN BIT(7) #define QPNP_PON_S2_RESET_ENABLE BIT(7) #define QPNP_PON_DELAY_BIT_SHIFT 6 +#define QPNP_PON_GEN2_DELAY_BIT_SHIFT 14 #define QPNP_PON_S1_TIMER_MASK (0xF) #define QPNP_PON_S2_TIMER_MASK (0x7) @@ -144,6 +145,8 @@ #define PON_S1_COUNT_MAX 0xF #define QPNP_PON_MIN_DBC_US (USEC_PER_SEC / 64) #define QPNP_PON_MAX_DBC_US (USEC_PER_SEC * 2) +#define QPNP_PON_GEN2_MIN_DBC_US 62 +#define QPNP_PON_GEN2_MAX_DBC_US (USEC_PER_SEC / 4) #define QPNP_KEY_STATUS_DELAY msecs_to_jiffies(250) @@ -370,23 +373,31 @@ EXPORT_SYMBOL(qpnp_pon_check_hard_reset_stored); static int qpnp_pon_set_dbc(struct qpnp_pon *pon, u32 delay) { int rc = 0; - u32 delay_reg; + u32 val; if (delay == pon->dbc) goto out; + if (pon->pon_input) mutex_lock(&pon->pon_input->mutex); - if (delay < QPNP_PON_MIN_DBC_US) - delay = QPNP_PON_MIN_DBC_US; - else if (delay > QPNP_PON_MAX_DBC_US) - delay = QPNP_PON_MAX_DBC_US; + if (is_pon_gen2(pon)) { + if (delay < QPNP_PON_GEN2_MIN_DBC_US) + delay = QPNP_PON_GEN2_MIN_DBC_US; + else if (delay > QPNP_PON_GEN2_MAX_DBC_US) + delay = QPNP_PON_GEN2_MAX_DBC_US; + val = (delay << QPNP_PON_GEN2_DELAY_BIT_SHIFT) / USEC_PER_SEC; + } else { + if (delay < QPNP_PON_MIN_DBC_US) + delay = QPNP_PON_MIN_DBC_US; + else if (delay > QPNP_PON_MAX_DBC_US) + delay = QPNP_PON_MAX_DBC_US; + val = (delay << QPNP_PON_DELAY_BIT_SHIFT) / USEC_PER_SEC; + } - delay_reg = (delay << QPNP_PON_DELAY_BIT_SHIFT) / USEC_PER_SEC; - delay_reg = ilog2(delay_reg); + val = ilog2(val); rc = qpnp_pon_masked_write(pon, QPNP_PON_DBC_CTL(pon), - QPNP_PON_DBC_DELAY_MASK(pon), - delay_reg); + QPNP_PON_DBC_DELAY_MASK(pon), val); if (rc) { dev_err(&pon->pdev->dev, "Unable to set PON debounce\n"); goto unlock; @@ -2195,8 +2206,7 @@ static int qpnp_pon_probe(struct platform_device *pdev) if (rc) { if (rc != -EINVAL) { dev_err(&pdev->dev, - "Unable to read debounce delay rc: %d\n", - rc); + "Unable to read debounce delay rc: %d\n", rc); return rc; } } else { From d166772079330846b23e5aad656c24a2ffa2027c Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Fri, 2 Dec 2016 14:24:52 -0800 Subject: [PATCH 3/3] Revert "input: powerkey: don't send dummy release event" This reverts commit d796ae6e8878daecf855d23658c546aeef506142 ("input: powerkey: don't send dummy release event") which was added as a workaround to ensure that keys held during resume were not artificially released by the input framework. This issue is already resolved by commit 768d9aa55740 ("Input: don't call input_dev_release_keys() in resume"). Change-Id: I542837eddce7cb1ffba55c3e5d6b2e5bd12c9e62 Signed-off-by: Subbaraman Narayanamurthy --- drivers/input/qpnp-power-on.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/input/qpnp-power-on.c b/drivers/input/qpnp-power-on.c index b9fe20c20b55..760c92a47a36 100644 --- a/drivers/input/qpnp-power-on.c +++ b/drivers/input/qpnp-power-on.c @@ -1206,8 +1206,6 @@ qpnp_pon_config_input(struct qpnp_pon *pon, struct qpnp_pon_config *cfg) pon->pon_input->phys = "qpnp_pon/input0"; } - /* don't send dummy release event when system resumes */ - __set_bit(INPUT_PROP_NO_DUMMY_RELEASE, pon->pon_input->propbit); input_set_capability(pon->pon_input, EV_KEY, cfg->key_code); return 0;