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Merge "ARM: dts: msm: Correct csiphy clocks and clock rates on msmcobalt"

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Linux Build Service Account 2016-10-06 19:45:39 -07:00 • committed by Gerrit - the friendly Code Review server
commit 8833b3623b
1 changed files with 18 additions and 9 deletions
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27
arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi
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@ -19,7 +19,10 @@
reg-names = "csiphy"; reg-names = "csiphy";
interrupts = <0 78 0>; interrupts = <0 78 0>;
interrupt-names = "csiphy"; interrupt-names = "csiphy";
clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, gdscr-supply = <&gdsc_camss_top>;
bimc_smmu-supply = <&gdsc_bimc_smmu>;
qcom,cam-vreg-name = "gdscr", "bimc_smmu";
clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
<&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>,
<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
<&clock_mmss clk_mmss_bimc_smmu_axi_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@ -33,13 +36,13 @@
<&clock_mmss clk_mmss_camss_ispif_ahb_clk>, <&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
<&clock_mmss clk_csiphy_clk_src>, <&clock_mmss clk_csiphy_clk_src>,
<&clock_mmss clk_mmss_camss_csiphy0_clk>; <&clock_mmss clk_mmss_camss_csiphy0_clk>;
clock-names = "mnoc_maxi", "mnoc_ahb", clock-names = "mmssnoc_axi", "mnoc_ahb",
"bmic_smmu_ahb", "bmic_smmu_axi", "bmic_smmu_ahb", "bmic_smmu_axi",
"camss_ahb_clk", "camss_top_ahb_clk", "camss_ahb_clk", "camss_top_ahb_clk",
"csi_src_clk", "csi_clk", "cphy_csid_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk",
"csiphy_timer_src_clk", "csiphy_timer_clk", "csiphy_timer_src_clk", "csiphy_timer_clk",
"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0 qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0
0 256000000 0>; 0 256000000 0>;
status = "ok"; status = "ok";
}; };
@ -51,7 +54,10 @@
reg-names = "csiphy"; reg-names = "csiphy";
interrupts = <0 79 0>; interrupts = <0 79 0>;
interrupt-names = "csiphy"; interrupt-names = "csiphy";
clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, gdscr-supply = <&gdsc_camss_top>;
bimc_smmu-supply = <&gdsc_bimc_smmu>;
qcom,cam-vreg-name = "gdscr", "bimc_smmu";
clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
<&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>,
<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
<&clock_mmss clk_mmss_bimc_smmu_axi_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@ -65,13 +71,13 @@
<&clock_mmss clk_mmss_camss_ispif_ahb_clk>, <&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
<&clock_mmss clk_csiphy_clk_src>, <&clock_mmss clk_csiphy_clk_src>,
<&clock_mmss clk_mmss_camss_csiphy1_clk>; <&clock_mmss clk_mmss_camss_csiphy1_clk>;
clock-names = "mnoc_maxi", "mnoc_ahb", clock-names = "mmssnoc_axi", "mnoc_ahb",
"bmic_smmu_ahb", "bmic_smmu_axi", "bmic_smmu_ahb", "bmic_smmu_axi",
"camss_ahb_clk", "camss_top_ahb_clk", "camss_ahb_clk", "camss_top_ahb_clk",
"csi_src_clk", "csi_clk", "cphy_csid_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk",
"csiphy_timer_src_clk", "csiphy_timer_clk", "csiphy_timer_src_clk", "csiphy_timer_clk",
"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0 qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0
0 256000000 0>; 0 256000000 0>;
status = "ok"; status = "ok";
}; };
@ -83,7 +89,10 @@
reg-names = "csiphy"; reg-names = "csiphy";
interrupts = <0 80 0>; interrupts = <0 80 0>;
interrupt-names = "csiphy"; interrupt-names = "csiphy";
clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, gdscr-supply = <&gdsc_camss_top>;
bimc_smmu-supply = <&gdsc_bimc_smmu>;
qcom,cam-vreg-name = "gdscr", "bimc_smmu";
clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
<&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>,
<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
<&clock_mmss clk_mmss_bimc_smmu_axi_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@ -97,13 +106,13 @@
<&clock_mmss clk_mmss_camss_ispif_ahb_clk>, <&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
<&clock_mmss clk_csiphy_clk_src>, <&clock_mmss clk_csiphy_clk_src>,
<&clock_mmss clk_mmss_camss_csiphy2_clk>; <&clock_mmss clk_mmss_camss_csiphy2_clk>;
clock-names = "mnoc_maxi", "mnoc_ahb", clock-names = "mmssnoc_axi", "mnoc_ahb",
"bmic_smmu_ahb", "bmic_smmu_axi", "bmic_smmu_ahb", "bmic_smmu_axi",
"camss_ahb_clk", "camss_top_ahb_clk", "camss_ahb_clk", "camss_top_ahb_clk",
"csi_src_clk", "csi_clk", "cphy_csid_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk",
"csiphy_timer_src_clk", "csiphy_timer_clk", "csiphy_timer_src_clk", "csiphy_timer_clk",
"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0 qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0
0 256000000 0>; 0 256000000 0>;
status = "ok"; status = "ok";
}; };