evie/android_kernel_oneplus_msm8998
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msm: kgsl: Explicitly set ISENSE clock rate for A540.

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On A540 ISENSE clock rate is controlled by GPU driver.

CRs-Fixed: 973565
Change-Id: Iab40cff01b6e65db51a4b793572714d2059a78ad
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
This commit is contained in:
Oleg Perelet 2016-04-28 11:16:35 -07:00 • committed by Kyle Yan
parent 7ea155dd2d
commit 8972d5e96e
2 changed files with 9 additions and 0 deletions
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7
drivers/gpu/msm/kgsl_pwrctrl.c
View file

@ -1685,6 +1685,7 @@ static int _get_clocks(struct kgsl_device *device)
const char *name;
struct property *prop;
pwr->isense_clk_indx = 0;
of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
int i;
@ -1703,6 +1704,8 @@ static int _get_clocks(struct kgsl_device *device)
return ret;
}
if (!strcmp(name, "isense_clk"))
pwr->isense_clk_indx = i;
break;
}
}
@ -1785,6 +1788,10 @@ int kgsl_pwrctrl_init(struct kgsl_device *device)
clk_set_rate(pwr->grp_clks[6],
clk_round_rate(pwr->grp_clks[6], KGSL_RBBMTIMER_CLK_FREQ));
if (pwr->isense_clk_indx)
clk_set_rate(pwr->grp_clks[pwr->isense_clk_indx],
KGSL_ISENSE_CLK_FREQ);
result = get_regulators(device);
if (result)
return result;

2
drivers/gpu/msm/kgsl_pwrctrl.h
View file

@ -36,6 +36,7 @@
#define KGSL_CONSTRAINT_PWR_MAXLEVELS 2
#define KGSL_RBBMTIMER_CLK_FREQ 19200000
#define KGSL_ISENSE_CLK_FREQ 200000000
/* Symbolic table for the constraint type */
#define KGSL_CONSTRAINT_TYPES \
@ -162,6 +163,7 @@ struct kgsl_pwrctrl {
struct clk *grp_clks[KGSL_MAX_CLKS];
struct clk *dummy_mx_clk;
struct clk *gpu_bimc_int_clk;
int isense_clk_indx;
unsigned long power_flags;
unsigned long ctrl_flags;
struct kgsl_pwrlevel pwrlevels[KGSL_MAX_PWRLEVELS];