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Merge branch 'for-3.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata

Browse source 
Pull libata fixes from Tejun Heo:
 "This contains three commits all of which are updates for specific
  devices which aren't too widespread.  Pretty limited scope and nothing
  too interesting or dangerous"

* 'for-3.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
  sata_fsl: save irqs while coalescing
  libata: apply behavioral quirks to sil3826 PMP
  sata, highbank: fix ordering of SGPIO signals
This commit is contained in:
Linus Torvalds 2013-08-23 10:59:42 -07:00
commit 89b53e50bd
3 changed files with 11 additions and 10 deletions
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12
drivers/ata/libata-pmp.c
View file

@ -289,24 +289,24 @@ static int sata_pmp_configure(struct ata_device *dev, int print_info)
/* Disable sending Early R_OK. /* Disable sending Early R_OK.
* With "cached read" HDD testing and multiple ports busy on a SATA * With "cached read" HDD testing and multiple ports busy on a SATA
* host controller, 3726 PMP will very rarely drop a deferred * host controller, 3x26 PMP will very rarely drop a deferred
* R_OK that was intended for the host. Symptom will be all * R_OK that was intended for the host. Symptom will be all
* 5 drives under test will timeout, get reset, and recover. * 5 drives under test will timeout, get reset, and recover.
*/ */
if (vendor == 0x1095 && devid == 0x3726) { if (vendor == 0x1095 && (devid == 0x3726 || devid == 0x3826)) {
u32 reg; u32 reg;
err_mask = sata_pmp_read(&ap->link, PMP_GSCR_SII_POL, &reg); err_mask = sata_pmp_read(&ap->link, PMP_GSCR_SII_POL, &reg);
if (err_mask) { if (err_mask) {
rc = -EIO; rc = -EIO;
reason = "failed to read Sil3726 Private Register"; reason = "failed to read Sil3x26 Private Register";
goto fail; goto fail;
} }
reg &= ~0x1; reg &= ~0x1;
err_mask = sata_pmp_write(&ap->link, PMP_GSCR_SII_POL, reg); err_mask = sata_pmp_write(&ap->link, PMP_GSCR_SII_POL, reg);
if (err_mask) { if (err_mask) {
rc = -EIO; rc = -EIO;
reason = "failed to write Sil3726 Private Register"; reason = "failed to write Sil3x26 Private Register";
goto fail; goto fail;
} }
} }
@ -383,8 +383,8 @@ static void sata_pmp_quirks(struct ata_port *ap)
u16 devid = sata_pmp_gscr_devid(gscr); u16 devid = sata_pmp_gscr_devid(gscr);
struct ata_link *link; struct ata_link *link;
if (vendor == 0x1095 && devid == 0x3726) { if (vendor == 0x1095 && (devid == 0x3726 || devid == 0x3826)) {
/* sil3726 quirks */ /* sil3x26 quirks */
ata_for_each_link(link, ap, EDGE) { ata_for_each_link(link, ap, EDGE) {
/* link reports offline after LPM */ /* link reports offline after LPM */
link->flags |= ATA_LFLAG_NO_LPM; link->flags |= ATA_LFLAG_NO_LPM;

5
drivers/ata/sata_fsl.c
View file

@ -293,6 +293,7 @@ static void fsl_sata_set_irq_coalescing(struct ata_host *host,
{ {
struct sata_fsl_host_priv *host_priv = host->private_data; struct sata_fsl_host_priv *host_priv = host->private_data;
void __iomem *hcr_base = host_priv->hcr_base; void __iomem *hcr_base = host_priv->hcr_base;
unsigned long flags;
if (count > ICC_MAX_INT_COUNT_THRESHOLD) if (count > ICC_MAX_INT_COUNT_THRESHOLD)
count = ICC_MAX_INT_COUNT_THRESHOLD; count = ICC_MAX_INT_COUNT_THRESHOLD;
@ -305,12 +306,12 @@ static void fsl_sata_set_irq_coalescing(struct ata_host *host,
(count > ICC_MIN_INT_COUNT_THRESHOLD)) (count > ICC_MIN_INT_COUNT_THRESHOLD))
ticks = ICC_SAFE_INT_TICKS; ticks = ICC_SAFE_INT_TICKS;
spin_lock(&host->lock); spin_lock_irqsave(&host->lock, flags);
iowrite32((count << 24 | ticks), hcr_base + ICC); iowrite32((count << 24 | ticks), hcr_base + ICC);
intr_coalescing_count = count; intr_coalescing_count = count;
intr_coalescing_ticks = ticks; intr_coalescing_ticks = ticks;
spin_unlock(&host->lock); spin_unlock_irqrestore(&host->lock, flags);
DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n", DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
intr_coalescing_count, intr_coalescing_ticks); intr_coalescing_count, intr_coalescing_ticks);

4
drivers/ata/sata_highbank.c
View file

@ -86,11 +86,11 @@ struct ecx_plat_data {
#define SGPIO_SIGNALS 3 #define SGPIO_SIGNALS 3
#define ECX_ACTIVITY_BITS 0x300000 #define ECX_ACTIVITY_BITS 0x300000
#define ECX_ACTIVITY_SHIFT 2 #define ECX_ACTIVITY_SHIFT 0
#define ECX_LOCATE_BITS 0x80000 #define ECX_LOCATE_BITS 0x80000
#define ECX_LOCATE_SHIFT 1 #define ECX_LOCATE_SHIFT 1
#define ECX_FAULT_BITS 0x400000 #define ECX_FAULT_BITS 0x400000
#define ECX_FAULT_SHIFT 0 #define ECX_FAULT_SHIFT 2
static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port, static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
u32 shift) u32 shift)
{ {