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drm/i915/skl: Restructured the gen6_set_rps_thresholds function

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Prior to SKL, the time period programmed in Up/Down EI & Up/Down
threshold registers was in units of 1.28 micro seconds. But for
SKL, the units have changed (1.333 micro seconds).
Have generalized the implementation of gen6_set_rps_thresholds function,
by removing the hard coding done in it as per 1.28 micro seconds.

v2: Renamed the local variables & removed superfluous comments (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Akash Goel 2015-03-06 11:07:18 +05:30 • committed by Daniel Vetter
parent 5704195c3f
commit 8a5864377b
1 changed files with 32 additions and 36 deletions
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68
drivers/gpu/drm/i915/intel_pm.c
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@ -3826,6 +3826,8 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
{ {
int new_power; int new_power;
u32 threshold_up = 0, threshold_down = 0; /* in % */
u32 ei_up = 0, ei_down = 0;
new_power = dev_priv->rps.power; new_power = dev_priv->rps.power;
switch (dev_priv->rps.power) { switch (dev_priv->rps.power) {
@ -3858,59 +3860,53 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
switch (new_power) { switch (new_power) {
case LOW_POWER: case LOW_POWER:
/* Upclock if more than 95% busy over 16ms */ /* Upclock if more than 95% busy over 16ms */
I915_WRITE(GEN6_RP_UP_EI, 12500); ei_up = 16000;
I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); threshold_up = 95;
/* Downclock if less than 85% busy over 32ms */ /* Downclock if less than 85% busy over 32ms */
I915_WRITE(GEN6_RP_DOWN_EI, 25000); ei_down = 32000;
I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); threshold_down = 85;
I915_WRITE(GEN6_RP_CONTROL,
GEN6_RP_MEDIA_TURBO |
GEN6_RP_MEDIA_HW_NORMAL_MODE |
GEN6_RP_MEDIA_IS_GFX |
GEN6_RP_ENABLE |
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
break; break;
case BETWEEN: case BETWEEN:
/* Upclock if more than 90% busy over 13ms */ /* Upclock if more than 90% busy over 13ms */
I915_WRITE(GEN6_RP_UP_EI, 10250); ei_up = 13000;
I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); threshold_up = 90;
/* Downclock if less than 75% busy over 32ms */ /* Downclock if less than 75% busy over 32ms */
I915_WRITE(GEN6_RP_DOWN_EI, 25000); ei_down = 32000;
I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); threshold_down = 75;
I915_WRITE(GEN6_RP_CONTROL,
GEN6_RP_MEDIA_TURBO |
GEN6_RP_MEDIA_HW_NORMAL_MODE |
GEN6_RP_MEDIA_IS_GFX |
GEN6_RP_ENABLE |
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
break; break;
case HIGH_POWER: case HIGH_POWER:
/* Upclock if more than 85% busy over 10ms */ /* Upclock if more than 85% busy over 10ms */
I915_WRITE(GEN6_RP_UP_EI, 8000); ei_up = 10000;
I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); threshold_up = 85;
/* Downclock if less than 60% busy over 32ms */ /* Downclock if less than 60% busy over 32ms */
I915_WRITE(GEN6_RP_DOWN_EI, 25000); ei_down = 32000;
I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); threshold_down = 60;
I915_WRITE(GEN6_RP_CONTROL,
GEN6_RP_MEDIA_TURBO |
GEN6_RP_MEDIA_HW_NORMAL_MODE |
GEN6_RP_MEDIA_IS_GFX |
GEN6_RP_ENABLE |
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
break; break;
} }
I915_WRITE(GEN6_RP_UP_EI,
GT_INTERVAL_FROM_US(dev_priv, ei_up));
I915_WRITE(GEN6_RP_UP_THRESHOLD,
GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
I915_WRITE(GEN6_RP_DOWN_EI,
GT_INTERVAL_FROM_US(dev_priv, ei_down));
I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
I915_WRITE(GEN6_RP_CONTROL,
GEN6_RP_MEDIA_TURBO |
GEN6_RP_MEDIA_HW_NORMAL_MODE |
GEN6_RP_MEDIA_IS_GFX |
GEN6_RP_ENABLE |
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
dev_priv->rps.power = new_power; dev_priv->rps.power = new_power;
dev_priv->rps.last_adj = 0; dev_priv->rps.last_adj = 0;
} }