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ARC: refactor atomic inline asm operands with symbolic names

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This reduces the diff in forth-coming patches and also helps understand
better the incremental changes to inline asm.

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta 2015-07-21 12:05:42 +03:00
parent f5959cb0c3
commit 8ac0665fb6
1 changed files with 17 additions and 15 deletions
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32
arch/arc/include/asm/atomic.h
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@ -26,22 +26,23 @@
#define ATOMIC_OP(op, c_op, asm_op) \ #define ATOMIC_OP(op, c_op, asm_op) \
static inline void atomic_##op(int i, atomic_t *v) \ static inline void atomic_##op(int i, atomic_t *v) \
{ \ { \
unsigned int temp; \ unsigned int val; \
\ \
__asm__ __volatile__( \ __asm__ __volatile__( \
"1: llock %0, [%1] \n" \ "1: llock %[val], [%[ctr]] \n" \
" " #asm_op " %0, %0, %2 \n" \ " " #asm_op " %[val], %[val], %[i] \n" \
" scond %0, [%1] \n" \ " scond %[val], [%[ctr]] \n" \
" bnz 1b \n" \ " bnz 1b \n" \
: "=&r"(temp) /* Early clobber, to prevent reg reuse */ \ : [val] "=&r" (val) /* Early clobber to prevent reg reuse */ \
: "r"(&v->counter), "ir"(i) \ : [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \
[i] "ir" (i) \
: "cc"); \ : "cc"); \
} \ } \
#define ATOMIC_OP_RETURN(op, c_op, asm_op) \ #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
static inline int atomic_##op##_return(int i, atomic_t *v) \ static inline int atomic_##op##_return(int i, atomic_t *v) \
{ \ { \
unsigned int temp; \ unsigned int val; \
\ \
/* \ /* \
* Explicit full memory barrier needed before/after as \ * Explicit full memory barrier needed before/after as \
@ -50,17 +51,18 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \
smp_mb(); \ smp_mb(); \
\ \
__asm__ __volatile__( \ __asm__ __volatile__( \
"1: llock %0, [%1] \n" \ "1: llock %[val], [%[ctr]] \n" \
" " #asm_op " %0, %0, %2 \n" \ " " #asm_op " %[val], %[val], %[i] \n" \
" scond %0, [%1] \n" \ " scond %[val], [%[ctr]] \n" \
" bnz 1b \n" \ " bnz 1b \n" \
: "=&r"(temp) \ : [val] "=&r" (val) \
: "r"(&v->counter), "ir"(i) \ : [ctr] "r" (&v->counter), \
[i] "ir" (i) \
: "cc"); \ : "cc"); \
\ \
smp_mb(); \ smp_mb(); \
\ \
return temp; \ return val; \
} }
#else /* !CONFIG_ARC_HAS_LLSC */ #else /* !CONFIG_ARC_HAS_LLSC */