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scsi: ufs-msm: rename all entities from "msm" to "qcom"

Browse source 
Since UFS is not used strictly in a specific set of targets but rather
its code is applicable to MSM, APQ, IPQ etc, everywhere where
there is a use of "msm" should be replaced with "qcom".

Change-Id: Ib96259bab6de506a40876c1c121a12bb75b655c1
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[subhashj@codeaurora.org: resolved merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This commit is contained in:
Yaniv Gardi 2014-09-01 17:31:46 +03:00 • committed by David Keitel
parent daf2901cea
commit 8c9b78c1e6
9 changed files with 950 additions and 940 deletions
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108
drivers/scsi/ufs/ufs-msm-phy-qmp-20nm.c
View file

@ -25,13 +25,14 @@
#include "ufs-msm-phy.h"
#include "ufs-msm-phy-qmp-20nm.h"
#define UFS_PHY_NAME "ufs_msm_phy_qmp_20nm"
#define UFS_PHY_NAME "ufs_phy_qmp_20nm"
static int ufs_msm_phy_qmp_20nm_phy_calibrate(struct ufs_msm_phy *ufs_msm_phy)
static
int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy)
{
struct ufs_msm_phy_calibration *tbl_A, *tbl_B;
struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
int tbl_size_A, tbl_size_B;
int rate = UFS_MSM_LIMIT_HS_RATE;
int rate = UFS_QCOM_LIMIT_HS_RATE;
int err;
tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
@ -40,52 +41,55 @@ static int ufs_msm_phy_qmp_20nm_phy_calibrate(struct ufs_msm_phy *ufs_msm_phy)
tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
tbl_B = phy_cal_table_rate_B;
err = ufs_msm_phy_calibrate(ufs_msm_phy, tbl_A, tbl_size_A,
err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
tbl_B, tbl_size_B, rate);
if (err)
dev_err(ufs_msm_phy->dev, "%s: ufs_msm_phy_calibrate() failed %d\n",
dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",
__func__, err);
return err;
}
static
void ufs_msm_phy_qmp_20nm_advertise_quirks(struct ufs_msm_phy *phy_common)
void ufs_qcom_phy_qmp_20nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
{
phy_common->quirks =
MSM_UFS_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
}
static int ufs_msm_phy_qmp_20nm_init(struct phy *generic_phy)
static int ufs_qcom_phy_qmp_20nm_init(struct phy *generic_phy)
{
struct ufs_msm_phy_qmp_20nm *phy = phy_get_drvdata(generic_phy);
struct ufs_msm_phy *phy_common = &phy->common_cfg;
struct ufs_qcom_phy_qmp_20nm *phy = phy_get_drvdata(generic_phy);
struct ufs_qcom_phy *phy_common = &phy->common_cfg;
int err = 0;
err = ufs_msm_phy_init_clks(generic_phy, phy_common);
err = ufs_qcom_phy_init_clks(generic_phy, phy_common);
if (err) {
dev_err(phy_common->dev, "%s: ufs_msm_phy_init_clks() failed %d\n",
dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
__func__, err);
goto out;
}
err = ufs_msm_phy_init_vregulators(generic_phy, phy_common);
err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);
if (err) {
dev_err(phy_common->dev, "%s: ufs_msm_phy_init_vregulators() failed %d\n",
dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
__func__, err);
goto out;
}
ufs_msm_phy_qmp_20nm_advertise_quirks(phy_common);
ufs_qcom_phy_qmp_20nm_advertise_quirks(phy_common);
out:
return err;
}
static
void ufs_msm_phy_qmp_20nm_power_control(struct ufs_msm_phy *phy, bool val)
void ufs_qcom_phy_qmp_20nm_power_control(struct ufs_qcom_phy *phy, bool val)
{
bool hibern8_exit_after_pwr_collapse = phy->quirks &
UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
if (val) {
writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
/*
@ -94,8 +98,7 @@ void ufs_msm_phy_qmp_20nm_power_control(struct ufs_msm_phy *phy, bool val)
*/
mb();
if (phy->quirks &
MSM_UFS_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE) {
if (hibern8_exit_after_pwr_collapse) {
/*
* Give atleast 1us delay after restoring PHY analog
* power.
@ -112,8 +115,7 @@ void ufs_msm_phy_qmp_20nm_power_control(struct ufs_msm_phy *phy, bool val)
mb();
}
} else {
if (phy->quirks &
MSM_UFS_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE) {
if (hibern8_exit_after_pwr_collapse) {
writel_relaxed(0x0A, phy->mmio +
QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
writel_relaxed(0x02, phy->mmio +
@ -135,14 +137,14 @@ void ufs_msm_phy_qmp_20nm_power_control(struct ufs_msm_phy *phy, bool val)
}
static
void ufs_msm_phy_qmp_20nm_set_tx_lane_enable(struct ufs_msm_phy *phy, u32 val)
void ufs_qcom_phy_qmp_20nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
{
writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK,
phy->mmio + UFS_PHY_TX_LANE_ENABLE);
mb();
}
static inline void ufs_msm_phy_qmp_20nm_start_serdes(struct ufs_msm_phy *phy)
static inline void ufs_qcom_phy_qmp_20nm_start_serdes(struct ufs_qcom_phy *phy)
{
u32 tmp;
@ -153,7 +155,7 @@ static inline void ufs_msm_phy_qmp_20nm_start_serdes(struct ufs_msm_phy *phy)
mb();
}
static int ufs_msm_phy_qmp_20nm_is_pcs_ready(struct ufs_msm_phy *phy_common)
static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
{
int err = 0;
u32 val;
@ -166,27 +168,27 @@ static int ufs_msm_phy_qmp_20nm_is_pcs_ready(struct ufs_msm_phy *phy_common)
return err;
}
struct phy_ops ufs_msm_phy_qmp_20nm_phy_ops = {
.init = ufs_msm_phy_qmp_20nm_init,
.exit = ufs_msm_phy_exit,
.power_on = ufs_msm_phy_power_on,
.power_off = ufs_msm_phy_power_off,
struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {
.init = ufs_qcom_phy_qmp_20nm_init,
.exit = ufs_qcom_phy_exit,
.power_on = ufs_qcom_phy_power_on,
.power_off = ufs_qcom_phy_power_off,
.owner = THIS_MODULE,
};
struct ufs_msm_phy_specific_ops phy_20nm_ops = {
.calibrate_phy = ufs_msm_phy_qmp_20nm_phy_calibrate,
.start_serdes = ufs_msm_phy_qmp_20nm_start_serdes,
.is_physical_coding_sublayer_ready = ufs_msm_phy_qmp_20nm_is_pcs_ready,
.set_tx_lane_enable = ufs_msm_phy_qmp_20nm_set_tx_lane_enable,
.power_control = ufs_msm_phy_qmp_20nm_power_control,
struct ufs_qcom_phy_specific_ops phy_20nm_ops = {
.calibrate_phy = ufs_qcom_phy_qmp_20nm_phy_calibrate,
.start_serdes = ufs_qcom_phy_qmp_20nm_start_serdes,
.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,
.set_tx_lane_enable = ufs_qcom_phy_qmp_20nm_set_tx_lane_enable,
.power_control = ufs_qcom_phy_qmp_20nm_power_control,
};
static int ufs_msm_phy_qmp_20nm_probe(struct platform_device *pdev)
static int ufs_qcom_phy_qmp_20nm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct phy *generic_phy;
struct ufs_msm_phy_qmp_20nm *phy;
struct ufs_qcom_phy_qmp_20nm *phy;
int err = 0;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
@ -196,11 +198,11 @@ static int ufs_msm_phy_qmp_20nm_probe(struct platform_device *pdev)
goto out;
}
generic_phy = ufs_msm_phy_generic_probe(pdev, &phy->common_cfg,
&ufs_msm_phy_qmp_20nm_phy_ops, &phy_20nm_ops);
generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
&ufs_qcom_phy_qmp_20nm_phy_ops, &phy_20nm_ops);
if (!generic_phy) {
dev_err(dev, "%s: ufs_msm_phy_generic_probe() failed\n",
dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
__func__);
err = -EIO;
goto out;
@ -215,38 +217,38 @@ out:
return err;
}
static int ufs_msm_phy_qmp_20nm_remove(struct platform_device *pdev)
static int ufs_qcom_phy_qmp_20nm_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct phy *generic_phy = to_phy(dev);
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
int err = 0;
err = ufs_msm_phy_remove(generic_phy, ufs_msm_phy);
err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);
if (err)
dev_err(dev, "%s: ufs_msm_phy_remove failed = %d\n",
dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",
__func__, err);
return err;
}
static const struct of_device_id ufs_msm_phy_qmp_20nm_of_match[] = {
static const struct of_device_id ufs_qcom_phy_qmp_20nm_of_match[] = {
{.compatible = "qcom,ufs-msm-phy-qmp-20nm"},
{},
};
MODULE_DEVICE_TABLE(of, ufs_msm_phy_qmp_20nm_of_match);
MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_20nm_of_match);
static struct platform_driver ufs_msm_phy_qmp_20nm_driver = {
.probe = ufs_msm_phy_qmp_20nm_probe,
.remove = ufs_msm_phy_qmp_20nm_remove,
static struct platform_driver ufs_qcom_phy_qmp_20nm_driver = {
.probe = ufs_qcom_phy_qmp_20nm_probe,
.remove = ufs_qcom_phy_qmp_20nm_remove,
.driver = {
.of_match_table = ufs_msm_phy_qmp_20nm_of_match,
.name = "ufs_msm_phy_qmp_20nm",
.of_match_table = ufs_qcom_phy_qmp_20nm_of_match,
.name = "ufs_qcom_phy_qmp_20nm",
.owner = THIS_MODULE,
},
};
module_platform_driver(ufs_msm_phy_qmp_20nm_driver);
module_platform_driver(ufs_qcom_phy_qmp_20nm_driver);
MODULE_DESCRIPTION("Universal Flash Storage (UFS) MSM PHY QMP 20nm");
MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 20nm");
MODULE_LICENSE("GPL v2");

178
drivers/scsi/ufs/ufs-msm-phy-qmp-20nm.h
View file

@ -12,12 +12,12 @@
*
*/
#ifndef UFS_MSM_PHY_QMP_20NM_H_
#define UFS_MSM_PHY_QMP_20NM_H_
#ifndef UFS_QCOM_PHY_QMP_20NM_H_
#define UFS_QCOM_PHY_QMP_20NM_H_
#include "ufs-msm-phy.h"
/* MSM UFS PHY control registers */
/* QCOM UFS PHY control registers */
#define COM_OFF(x) (0x000 + x)
#define PHY_OFF(x) (0xC00 + x)
@ -119,98 +119,98 @@
* This structure represents the 20nm specific phy.
* common_cfg MUST remain the first field in this structure
* in case extra fields are added. This way, when calling
* get_ufs_msm_phy() of generic phy, we can extract the
* common phy structure (struct ufs_msm_phy) out of it
* get_ufs_qcom_phy() of generic phy, we can extract the
* common phy structure (struct ufs_qcom_phy) out of it
* regardless of the relevant specific phy.
*/
struct ufs_msm_phy_qmp_20nm {
struct ufs_msm_phy common_cfg;
struct ufs_qcom_phy_qmp_20nm {
struct ufs_qcom_phy common_cfg;
};
static struct ufs_msm_phy_calibration phy_cal_table_rate_A[] = {
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(0), 0x2F),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(0), 0x20),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(1), 0x2F),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(1), 0x20),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(0), 0x2F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(0), 0x20),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(1), 0x2F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(1), 0x20),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
};
static struct ufs_msm_phy_calibration phy_cal_table_rate_B[] = {
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
};
#endif

133
drivers/scsi/ufs/ufs-msm-phy-qmp-28nm.c
View file

@ -26,10 +26,10 @@
#include "ufs-msm-phy.h"
#include "ufs-msm-phy-qmp-28nm.h"
#define UFS_PHY_NAME "ufs_msm_phy_qmp_28nm"
#define UFS_PHY_NAME "ufs_qcom_phy_qmp_28nm"
static
void ufs_msm_phy_qmp_28nm_power_control(struct ufs_msm_phy *phy, bool val)
void ufs_qcom_phy_qmp_28nm_power_control(struct ufs_qcom_phy *phy, bool val)
{
if (val) {
writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
@ -40,7 +40,7 @@ void ufs_msm_phy_qmp_28nm_power_control(struct ufs_msm_phy *phy, bool val)
* SIGDET.
*/
mb();
if (phy->quirks & MSM_UFS_PHY_DIS_SIGDET_BEFORE_PWR_COLLAPSE) {
if (phy->quirks & UFS_QCOM_PHY_DIS_SIGDET_BEFORE_PWR_COLLAPSE) {
writel_relaxed(0xC0,
phy->mmio + QSERDES_RX_SIGDET_CNTRL(0));
writel_relaxed(0xC0,
@ -52,7 +52,8 @@ void ufs_msm_phy_qmp_28nm_power_control(struct ufs_msm_phy *phy, bool val)
mb();
}
} else {
if (phy->quirks & MSM_UFS_PHY_DIS_SIGDET_BEFORE_PWR_COLLAPSE) {
if (phy->quirks &
UFS_QCOM_PHY_DIS_SIGDET_BEFORE_PWR_COLLAPSE) {
writel_relaxed(0x0,
phy->mmio + QSERDES_RX_SIGDET_CNTRL(0));
writel_relaxed(0x0,
@ -73,46 +74,46 @@ void ufs_msm_phy_qmp_28nm_power_control(struct ufs_msm_phy *phy, bool val)
}
static
void ufs_msm_phy_qmp_28nm_advertise_quirks(struct ufs_msm_phy *phy_common)
void ufs_qcom_phy_qmp_28nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
{
phy_common->quirks = MSM_UFS_PHY_QUIRK_CFG_RESTORE
| MSM_UFS_PHY_DIS_SIGDET_BEFORE_PWR_COLLAPSE;
phy_common->quirks = UFS_QCOM_PHY_QUIRK_CFG_RESTORE
| UFS_QCOM_PHY_DIS_SIGDET_BEFORE_PWR_COLLAPSE;
}
static int ufs_msm_phy_qmp_28nm_init(struct phy *generic_phy)
static int ufs_qcom_phy_qmp_28nm_init(struct phy *generic_phy)
{
struct ufs_msm_phy_qmp_28nm *phy = phy_get_drvdata(generic_phy);
struct ufs_msm_phy *phy_common = &phy->common_cfg;
struct ufs_qcom_phy_qmp_28nm *phy = phy_get_drvdata(generic_phy);
struct ufs_qcom_phy *phy_common = &phy->common_cfg;
int err = 0;
err = ufs_msm_phy_init_clks(generic_phy, phy_common);
err = ufs_qcom_phy_init_clks(generic_phy, phy_common);
if (err) {
dev_err(phy_common->dev, "%s: ufs_msm_phy_init_clks() failed %d\n",
dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
__func__, err);
goto out;
}
err = ufs_msm_phy_init_vregulators(generic_phy, phy_common);
err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);
if (err) {
dev_err(phy_common->dev, "%s: ufs_msm_phy_init_vregulators() failed %d\n",
dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
__func__, err);
goto out;
}
ufs_msm_phy_qmp_28nm_advertise_quirks(phy_common);
ufs_qcom_phy_qmp_28nm_advertise_quirks(phy_common);
out:
return err;
}
static int ufs_msm_phy_qmp_28nm_calibrate(struct ufs_msm_phy *ufs_msm_phy)
static int ufs_qcom_phy_qmp_28nm_calibrate(struct ufs_qcom_phy *ufs_qcom_phy)
{
struct ufs_msm_phy_calibration *tbl_A, *tbl_B;
struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
int tbl_size_A, tbl_size_B;
int rate = UFS_MSM_LIMIT_HS_RATE;
u8 major = ufs_msm_phy->host_ctrl_rev_major;
u16 minor = ufs_msm_phy->host_ctrl_rev_minor;
u16 step = ufs_msm_phy->host_ctrl_rev_step;
int rate = UFS_QCOM_LIMIT_HS_RATE;
u8 major = ufs_qcom_phy->host_ctrl_rev_major;
u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
u16 step = ufs_qcom_phy->host_ctrl_rev_step;
int err;
if ((major == 0x1) && (minor == 0x001) && (step == 0x0000)) {
@ -126,17 +127,17 @@ static int ufs_msm_phy_qmp_28nm_calibrate(struct ufs_msm_phy *ufs_msm_phy)
tbl_B = phy_cal_table_rate_B;
tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
err = ufs_msm_phy_calibrate(ufs_msm_phy, tbl_A, tbl_size_A,
err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
tbl_B, tbl_size_B, rate);
if (err)
dev_err(ufs_msm_phy->dev, "%s: ufs_msm_phy_calibrate() failed %d\n",
dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",
__func__, err);
return err;
}
static
u32 ufs_msm_phy_qmp_28nm_read_attr(struct ufs_msm_phy *phy_common, u32 attr)
u32 ufs_qcom_phy_qmp_28nm_read_attr(struct ufs_qcom_phy *phy_common, u32 attr)
{
u32 l0, l1;
@ -160,8 +161,8 @@ u32 ufs_msm_phy_qmp_28nm_read_attr(struct ufs_msm_phy *phy_common, u32 attr)
}
static void
ufs_msm_phy_qmp_28nm_write_attr(struct ufs_msm_phy *phy_common,
u32 attr, u32 val)
ufs_qcom_phy_qmp_28nm_write_attr(struct ufs_qcom_phy *phy_common,
u32 attr, u32 val)
{
writel_relaxed(attr, phy_common->mmio + UFS_PHY_RMMI_ATTRID);
writel_relaxed(val, phy_common->mmio + UFS_PHY_RMMI_ATTRWRVAL);
@ -181,7 +182,7 @@ ufs_msm_phy_qmp_28nm_write_attr(struct ufs_msm_phy *phy_common,
}
static
void ufs_msm_phy_qmp_28nm_save_configuration(struct ufs_msm_phy *phy_common)
void ufs_qcom_phy_qmp_28nm_save_configuration(struct ufs_qcom_phy *phy_common)
{
int i;
@ -192,29 +193,29 @@ void ufs_msm_phy_qmp_28nm_save_configuration(struct ufs_msm_phy *phy_common)
for (i = 0; i < ARRAY_SIZE(cached_phy_attr); i++)
cached_phy_attr[i].value =
ufs_msm_phy_qmp_28nm_read_attr(phy_common,
ufs_qcom_phy_qmp_28nm_read_attr(phy_common,
cached_phy_attr[i].att);
}
static
void ufs_msm_phy_qmp_28nm_restore_configuration(struct ufs_msm_phy *phy_common)
static void
ufs_qcom_phy_qmp_28nm_restore_configuration(struct ufs_qcom_phy *phy_common)
{
int i;
for (i = 0; i < ARRAY_SIZE(cached_phy_attr); i++)
ufs_msm_phy_qmp_28nm_write_attr(phy_common,
ufs_qcom_phy_qmp_28nm_write_attr(phy_common,
cached_phy_attr[i].att, cached_phy_attr[i].value);
}
static
void ufs_msm_phy_qmp_28nm_set_tx_lane_enable(struct ufs_msm_phy *phy, u32 val)
void ufs_qcom_phy_qmp_28nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
{
writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK,
phy->mmio + UFS_PHY_TX_LANE_ENABLE);
mb();
}
static inline void ufs_msm_phy_qmp_28nm_start_serdes(struct ufs_msm_phy *phy)
static inline void ufs_qcom_phy_qmp_28nm_start_serdes(struct ufs_qcom_phy *phy)
{
u32 tmp;
@ -225,7 +226,7 @@ static inline void ufs_msm_phy_qmp_28nm_start_serdes(struct ufs_msm_phy *phy)
mb();
}
static int ufs_msm_phy_qmp_28nm_is_pcs_ready(struct ufs_msm_phy *phy_common)
static int ufs_qcom_phy_qmp_28nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
{
int err = 0;
u32 val;
@ -239,27 +240,27 @@ static int ufs_msm_phy_qmp_28nm_is_pcs_ready(struct ufs_msm_phy *phy_common)
return err;
}
struct phy_ops ufs_msm_phy_qmp_28nm_phy_ops = {
.init = ufs_msm_phy_qmp_28nm_init,
.exit = ufs_msm_phy_exit,
.power_on = ufs_msm_phy_power_on,
.power_off = ufs_msm_phy_power_off,
struct phy_ops ufs_qcom_phy_qmp_28nm_phy_ops = {
.init = ufs_qcom_phy_qmp_28nm_init,
.exit = ufs_qcom_phy_exit,
.power_on = ufs_qcom_phy_power_on,
.power_off = ufs_qcom_phy_power_off,
.owner = THIS_MODULE,
};
struct ufs_msm_phy_specific_ops phy_28nm_ops = {
.calibrate_phy = ufs_msm_phy_qmp_28nm_calibrate,
.start_serdes = ufs_msm_phy_qmp_28nm_start_serdes,
.save_configuration = ufs_msm_phy_qmp_28nm_save_configuration,
.restore_configuration = ufs_msm_phy_qmp_28nm_restore_configuration,
.is_physical_coding_sublayer_ready = ufs_msm_phy_qmp_28nm_is_pcs_ready,
.set_tx_lane_enable = ufs_msm_phy_qmp_28nm_set_tx_lane_enable,
.power_control = ufs_msm_phy_qmp_28nm_power_control,
struct ufs_qcom_phy_specific_ops phy_28nm_ops = {
.calibrate_phy = ufs_qcom_phy_qmp_28nm_calibrate,
.start_serdes = ufs_qcom_phy_qmp_28nm_start_serdes,
.save_configuration = ufs_qcom_phy_qmp_28nm_save_configuration,
.restore_configuration = ufs_qcom_phy_qmp_28nm_restore_configuration,
.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_28nm_is_pcs_ready,
.set_tx_lane_enable = ufs_qcom_phy_qmp_28nm_set_tx_lane_enable,
.power_control = ufs_qcom_phy_qmp_28nm_power_control,
};
static int ufs_msm_phy_qmp_28nm_probe(struct platform_device *pdev)
static int ufs_qcom_phy_qmp_28nm_probe(struct platform_device *pdev)
{
struct ufs_msm_phy_qmp_28nm *phy;
struct ufs_qcom_phy_qmp_28nm *phy;
struct device *dev = &pdev->dev;
int err = 0;
struct phy *generic_phy;
@ -272,15 +273,15 @@ static int ufs_msm_phy_qmp_28nm_probe(struct platform_device *pdev)
}
phy->common_cfg.cached_regs =
(struct ufs_msm_phy_calibration *)cached_phy_regs;
(struct ufs_qcom_phy_calibration *)cached_phy_regs;
phy->common_cfg.cached_regs_table_size =
ARRAY_SIZE(cached_phy_regs);
generic_phy = ufs_msm_phy_generic_probe(pdev, &phy->common_cfg,
&ufs_msm_phy_qmp_28nm_phy_ops, &phy_28nm_ops);
generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
&ufs_qcom_phy_qmp_28nm_phy_ops, &phy_28nm_ops);
if (!generic_phy) {
dev_err(dev, "%s: ufs_msm_phy_generic_probe() failed\n",
dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
__func__);
err = -EIO;
goto out;
@ -295,38 +296,38 @@ out:
return err;
}
static int ufs_msm_phy_qmp_28nm_remove(struct platform_device *pdev)
static int ufs_qcom_phy_qmp_28nm_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct phy *generic_phy = to_phy(dev);
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
int err = 0;
err = ufs_msm_phy_remove(generic_phy, ufs_msm_phy);
err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);
if (err)
dev_err(dev, "%s: ufs_msm_phy_remove failed = %d\n",
dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",
__func__, err);
return err;
}
static const struct of_device_id ufs_msm_phy_qmp_28nm_of_match[] = {
static const struct of_device_id ufs_qcom_phy_qmp_28nm_of_match[] = {
{.compatible = "qcom,ufs-msm-phy-qmp-28nm"},
{},
};
MODULE_DEVICE_TABLE(of, ufs_msm_phy_qmp_28nm_of_match);
MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_28nm_of_match);
static struct platform_driver ufs_msm_phy_qmp_28nm_driver = {
.probe = ufs_msm_phy_qmp_28nm_probe,
.remove = ufs_msm_phy_qmp_28nm_remove,
static struct platform_driver ufs_qcom_phy_qmp_28nm_driver = {
.probe = ufs_qcom_phy_qmp_28nm_probe,
.remove = ufs_qcom_phy_qmp_28nm_remove,
.driver = {
.of_match_table = ufs_msm_phy_qmp_28nm_of_match,
.name = "ufs_msm_phy_qmp_28nm",
.of_match_table = ufs_qcom_phy_qmp_28nm_of_match,
.name = "ufs_qcom_phy_qmp_28nm",
.owner = THIS_MODULE,
},
};
module_platform_driver(ufs_msm_phy_qmp_28nm_driver);
module_platform_driver(ufs_qcom_phy_qmp_28nm_driver);
MODULE_DESCRIPTION("Universal Flash Storage (UFS) MSM PHY QMP 28nm");
MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 28nm");
MODULE_LICENSE("GPL v2");

655
drivers/scsi/ufs/ufs-msm-phy-qmp-28nm.h
View file

@ -12,12 +12,12 @@
*
*/
#ifndef UFS_MSM_PHY_QMP_28NM_H_
#define UFS_MSM_PHY_QMP_28NM_H_
#ifndef UFS_QCOM_PHY_QMP_28NM_H_
#define UFS_QCOM_PHY_QMP_28NM_H_
#include "ufs-msm-phy.h"
/* MSM UFS PHY control registers */
/* QCOM UFS PHY control registers */
#define COM_OFF(x) (0x000 + x)
#define PHY_OFF(x) (0x700 + x)
@ -275,363 +275,366 @@
* This structure represents the 28nm specific phy.
* common_cfg MUST remain the first field in this structure
* in case extra fields are added. This way, when calling
* get_ufs_msm_phy() of generic phy, we can extract the
* common phy structure (struct ufs_msm_phy) out of it
* get_ufs_qcom_phy() of generic phy, we can extract the
* common phy structure (struct ufs_qcom_phy) out of it
* regardless of the relevant specific phy.
*/
struct ufs_msm_phy_qmp_28nm {
struct ufs_msm_phy common_cfg;
struct ufs_qcom_phy_qmp_28nm {
struct ufs_qcom_phy common_cfg;
};
static struct ufs_msm_phy_calibration phy_cal_table_ctrl_1_1_0_rate_A[] = {
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xFF),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x24),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x08),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x67),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x10),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x13),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(0), 0x43),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(1), 0x43),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(0), 0x22),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x12),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x2a),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(1), 0x22),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x12),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x2a),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(0), 0xC0),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(1), 0xC0),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(0), 0x07),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(1), 0x07),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_PWM_G1_CLK_DIVIDER, 0x50),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_PWM_G2_CLK_DIVIDER, 0x28),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_PWM_G3_CLK_DIVIDER, 0x10),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_PWM_G4_CLK_DIVIDER, 0x08),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER, 0xa8),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER, 0x54),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER, 0x2a),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER, 0x15),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_OMC_STATUS_RDVAL, 0xff),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_TIME, 0x1f),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_GRANULARITY, 0x00),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TSYNC_RSYNC_CNTL, 0x03),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x1a),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL, 0x00),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL, 0x00),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CFG_CHANGE_CNT_VAL, 0x09),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_SYNC_WAIT_TIME, 0x30),
UFS_MSM_PHY_CAL_ENTRY(
static struct ufs_qcom_phy_calibration phy_cal_table_ctrl_1_1_0_rate_A[] = {
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xFF),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x24),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x08),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x67),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x10),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x13),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(0), 0x43),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(1), 0x43),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(0), 0x22),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x12),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x2a),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(1), 0x22),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x12),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x2a),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(0), 0xC0),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(1), 0xC0),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(0), 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(1), 0x07),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G1_CLK_DIVIDER, 0x50),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G2_CLK_DIVIDER, 0x28),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G3_CLK_DIVIDER, 0x10),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G4_CLK_DIVIDER, 0x08),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER, 0xa8),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER, 0x54),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER, 0x2a),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER, 0x15),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_OMC_STATUS_RDVAL, 0xff),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_TIME, 0x1f),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_GRANULARITY, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TSYNC_RSYNC_CNTL, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x1a),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CFG_CHANGE_CNT_VAL, 0x09),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYNC_WAIT_TIME, 0x30),
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY, 0x08),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY, 0x04),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY, 0xc8),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY, 0x10),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(0), 0x07),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(0), 0x07),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(1), 0x07),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(1), 0x07),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_RES_TRIM_OFFSET, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_BGTC, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_AMP_OS, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(0), 0x0f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(1), 0x0f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(0), 0x04),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(1), 0x04),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(0), 0x05),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(1), 0x05),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_MSB, 0x07),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_LSB, 0x80),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x27),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x00),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CONTROLSYM_ONE_HOT_DISABLE, 0x00),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RETIME_BUFFER_EN, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_PWMGEAR_CAPABILITY, 0x04),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_AMPLITUDE_CAPABILITY, 0x03),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_EXTERNALSYNC_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(0), 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(0), 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(1), 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(1), 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_TRIM_OFFSET, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BGTC, 0x0f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_AMP_OS, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(0), 0x0f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(1), 0x0f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(0), 0x04),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(1), 0x04),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(0), 0x05),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(1), 0x05),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_MSB, 0x07),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_LSB, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x27),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CONTROLSYM_ONE_HOT_DISABLE, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RETIME_BUFFER_EN, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_PWMGEAR_CAPABILITY, 0x04),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_AMPLITUDE_CAPABILITY, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_EXTERNALSYNC_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_TX_HS_UNTERMINATED_LINE_DRIVE_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_TX_LS_TERMINATED_LINE_DRIVE_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_HIBERN8TIME_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_PWMGEAR_CAPABILITY, 0x04),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_UNTERMINATED_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_TERMINATED_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G1_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HIBERN8TIME_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWMGEAR_CAPABILITY, 0x04),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_UNTERMINATED_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_TERMINATED_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G1_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_RX_HS_G1_PREPARE_LENGTH_CAPABILITY, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_PREPARE_LENGTH_CAPABILITY, 0x09),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HIBERN8TIME_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G2_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G3_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_PREPARE_LENGTH_CAPABILITY, 0x09),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HIBERN8TIME_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G2_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G3_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_RX_HS_G2_PREPARE_LENGTH_CAPABILITY, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_RX_HS_G3_PREPARE_LENGTH_CAPABILITY, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(0), 0x09),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(0), 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(0), 0x73),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(0), 0x05),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(0), 0x22),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(0), 0x0a),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(0), 0x06),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(0), 0x09),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(0), 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(0), 0x73),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(0), 0x05),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(0), 0x22),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(0), 0x0a),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(0), 0x06),
UFS_QCOM_PHY_CAL_ENTRY(
QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE(0), 0x35),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(1), 0x09),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(1), 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(1), 0x73),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(1), 0x05),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(1), 0x22),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(1), 0x0a),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(1), 0x06),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(1), 0x09),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(1), 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(1), 0x73),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(1), 0x05),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(1), 0x22),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(1), 0x0a),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(1), 0x06),
UFS_QCOM_PHY_CAL_ENTRY(
QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE(1), 0x35),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MODE, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_IE_TRIM, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_IP_TRIM, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_IN_SYNC_SEL, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_TEST_UPDN_RESTRIMSTEP, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_FAUX_EN, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MODE, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_IE_TRIM, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_IP_TRIM, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_IN_SYNC_SEL, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_TEST_UPDN_RESTRIMSTEP, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_FAUX_EN, 0x00),
};
static struct ufs_msm_phy_calibration phy_cal_table_ctrl_1_1_1_rate_A[] = {
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0x43),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x24),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x08),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x10),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(0), 0x43),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(1), 0x43),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(0), 0x40),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(1), 0x40),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(0), 0xC0),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(1), 0xC0),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(0), 0x07),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(1), 0x07),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_PWM_G1_CLK_DIVIDER, 0x30),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_PWM_G2_CLK_DIVIDER, 0x18),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_PWM_G3_CLK_DIVIDER, 0x0c),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_PWM_G4_CLK_DIVIDER, 0x06),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER, 0xa8),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER, 0x54),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER, 0x2a),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER, 0x15),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_OMC_STATUS_RDVAL, 0xff),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_TIME, 0x1f),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_GRANULARITY, 0x00),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TSYNC_RSYNC_CNTL, 0x03),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x1a),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL, 0x00),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL, 0x00),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CFG_CHANGE_CNT_VAL, 0x09),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_SYNC_WAIT_TIME, 0x30),
UFS_MSM_PHY_CAL_ENTRY(
static struct ufs_qcom_phy_calibration phy_cal_table_ctrl_1_1_1_rate_A[] = {
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0x43),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x24),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x08),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x10),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(0), 0x43),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(1), 0x43),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(0), 0x40),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(1), 0x40),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(0), 0xC0),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(1), 0xC0),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(0), 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(1), 0x07),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G1_CLK_DIVIDER, 0x30),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G2_CLK_DIVIDER, 0x18),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G3_CLK_DIVIDER, 0x0c),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PWM_G4_CLK_DIVIDER, 0x06),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER, 0xa8),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER, 0x54),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER, 0x2a),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER, 0x15),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_OMC_STATUS_RDVAL, 0xff),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_TIME, 0x1f),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_LINE_RESET_GRANULARITY, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TSYNC_RSYNC_CNTL, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x1a),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CFG_CHANGE_CNT_VAL, 0x09),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYNC_WAIT_TIME, 0x30),
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY, 0x08),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY, 0x04),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY, 0xc8),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY, 0x10),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(0), 0x1f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(0), 0x17),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(1), 0x1f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(1), 0x17),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x07),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x07),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_RES_TRIM_OFFSET, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_BGTC, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_AMP_OS, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(0), 0x05),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(1), 0x05),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_MSB, 0x07),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_LSB, 0x80),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x27),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x00),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_CONTROLSYM_ONE_HOT_DISABLE, 0x00),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RETIME_BUFFER_EN, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_PWMGEAR_CAPABILITY, 0x04),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_AMPLITUDE_CAPABILITY, 0x03),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_EXTERNALSYNC_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(0), 0x1f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(0), 0x17),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1(1), 0x1f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2(1), 0x17),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL3(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x0f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_TRIM_OFFSET, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BGTC, 0x0f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_AMP_OS, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_DRV_LVL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_BIST_MODE_LANENO(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TX_EMP_POST1_LVL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(0), 0x05),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_EN(1), 0x05),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_MSB, 0x07),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_100US_SYSCLK_STEPS_LSB, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x27),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_CONTROLSYM_ONE_HOT_DISABLE, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RETIME_BUFFER_EN, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_PWMGEAR_CAPABILITY, 0x04),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_AMPLITUDE_CAPABILITY, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_EXTERNALSYNC_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_TX_HS_UNTERMINATED_LINE_DRIVE_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(
UFS_PHY_TX_LS_TERMINATED_LINE_DRIVE_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_TX_HIBERN8TIME_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_PWMGEAR_CAPABILITY, 0x04),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_UNTERMINATED_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_TERMINATED_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G1_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G1_PREPARE_LENGTH_CAPABILITY, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_PREPARE_LENGTH_CAPABILITY, 0x0a),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HIBERN8TIME_CAPABILITY, 0x01),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G2_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G3_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G2_PREPARE_LENGTH_CAPABILITY, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G3_PREPARE_LENGTH_CAPABILITY, 0x0f),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(0), 0x09),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(0), 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(0), 0x51),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(0), 0x05),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(0), 0x22),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(0), 0x0a),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(0), 0x06),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HIBERN8TIME_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWMGEAR_CAPABILITY, 0x04),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_UNTERMINATED_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_TERMINATED_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_REF_CLOCK_SHARED_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G1_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G1_PREPARE_LENGTH_CAPABILITY,
0x0f),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_LS_PREPARE_LENGTH_CAPABILITY, 0x0a),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HIBERN8TIME_CAPABILITY, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G2_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G3_SYNC_LENGTH_CAPABILITY, 0x48),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G2_PREPARE_LENGTH_CAPABILITY,
0x0f),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G3_PREPARE_LENGTH_CAPABILITY,
0x0f),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(0), 0x09),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(0), 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(0), 0x51),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(0), 0x05),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(0), 0x22),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(0), 0x0a),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(0), 0x06),
UFS_QCOM_PHY_CAL_ENTRY(
QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE(0), 0x35),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(0), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(1), 0x09),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(1), 0x01),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(1), 0x51),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(1), 0x05),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(1), 0x22),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(1), 0x0a),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(1), 0x06),
UFS_MSM_PHY_CAL_ENTRY(
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(0), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_CLKBUF_ENABLE(1), 0x09),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RESET_TSYNC_EN(1), 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_RES_CODE(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_SERDES_BYP_EN_OUT(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_REC_DETECT_LVL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_TRAN_DRVR_EMP_EN(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_CONTROL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_AUX_DATA_TCODE(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RCLK_AUXDATA_SEL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_EQ_CONTROL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(1), 0x51),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE(1), 0x05),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_FREEZE_UP_DN(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_EIGHTH(1), 0x22),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_GAIN(1), 0x0a),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_GAIN(1), 0x06),
UFS_QCOM_PHY_CAL_ENTRY(
QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE(1), 0x35),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(1), 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MODE, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_IE_TRIM, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_IP_TRIM, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_IN_SYNC_SEL, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_TEST_UPDN_RESTRIMSTEP, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_FAUX_EN, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x08),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x08),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FO_TO_SO_DELAY(1), 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MODE, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_IE_TRIM, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_IP_TRIM, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_IN_SYNC_SEL, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_TEST_UPDN_RESTRIMSTEP, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_FAUX_EN, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x08),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x08),
};
static struct ufs_msm_phy_calibration phy_cal_table_rate_B[] = {
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1E),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
};
static struct ufs_msm_phy_calibration cached_phy_regs[] = {
static struct ufs_qcom_phy_calibration cached_phy_regs[] = {
{QSERDES_COM_PLL_CRCTRL},
{QSERDES_COM_PLL_CNTRL},
{QSERDES_COM_SYSCLK_EN_SEL},
@ -702,7 +705,7 @@ static struct ufs_msm_phy_calibration cached_phy_regs[] = {
{QSERDES_COM_PLL_AMP_OS},
};
static struct ufs_msm_phy_stored_attributes cached_phy_attr[] = {
static struct ufs_qcom_phy_stored_attributes cached_phy_attr[] = {
{TX_MODE},
{TX_HSRATE_SERIES},
{TX_HSGEAR},

270
drivers/scsi/ufs/ufs-msm-phy.c
View file

@ -24,23 +24,24 @@
#include "ufs-msm-phy.h"
int ufs_msm_phy_calibrate(struct ufs_msm_phy *ufs_msm_phy,
struct ufs_msm_phy_calibration *tbl_A, int tbl_size_A,
struct ufs_msm_phy_calibration *tbl_B, int tbl_size_B,
int rate)
int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
struct ufs_qcom_phy_calibration *tbl_A,
int tbl_size_A,
struct ufs_qcom_phy_calibration *tbl_B,
int tbl_size_B, int rate)
{
int i;
int ret = 0;
if (!tbl_A) {
dev_err(ufs_msm_phy->dev, "%s: tbl_A is NULL", __func__);
dev_err(ufs_qcom_phy->dev, "%s: tbl_A is NULL", __func__);
ret = EINVAL;
goto out;
}
for (i = 0; i < tbl_size_A; i++)
writel_relaxed(tbl_A[i].cfg_value,
ufs_msm_phy->mmio + tbl_A[i].reg_offset);
ufs_qcom_phy->mmio + tbl_A[i].reg_offset);
/*
* In case we would like to work in rate B, we need
@ -50,7 +51,7 @@ int ufs_msm_phy_calibrate(struct ufs_msm_phy *ufs_msm_phy,
*/
if (rate == PA_HS_MODE_B) {
if (!tbl_B) {
dev_err(ufs_msm_phy->dev, "%s: tbl_B is NULL",
dev_err(ufs_qcom_phy->dev, "%s: tbl_B is NULL",
__func__);
ret = EINVAL;
goto out;
@ -58,7 +59,7 @@ int ufs_msm_phy_calibrate(struct ufs_msm_phy *ufs_msm_phy,
for (i = 0; i < tbl_size_B; i++)
writel_relaxed(tbl_B[i].cfg_value,
ufs_msm_phy->mmio + tbl_B[i].reg_offset);
ufs_qcom_phy->mmio + tbl_B[i].reg_offset);
}
/* flush buffered writes */
@ -68,17 +69,17 @@ out:
return ret;
}
struct phy *ufs_msm_phy_generic_probe(struct platform_device *pdev,
struct ufs_msm_phy *common_cfg,
struct phy_ops *ufs_msm_phy_gen_ops,
struct ufs_msm_phy_specific_ops *phy_spec_ops)
struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
struct ufs_qcom_phy *common_cfg,
struct phy_ops *ufs_qcom_phy_gen_ops,
struct ufs_qcom_phy_specific_ops *phy_spec_ops)
{
int err;
struct device *dev = &pdev->dev;
struct phy *generic_phy = NULL;
struct phy_provider *phy_provider;
err = ufs_msm_phy_base_init(pdev, common_cfg);
err = ufs_qcom_phy_base_init(pdev, common_cfg);
if (err) {
dev_err(dev, "%s: phy base init failed %d\n", __func__, err);
goto out;
@ -91,7 +92,7 @@ struct phy *ufs_msm_phy_generic_probe(struct platform_device *pdev,
goto out;
}
generic_phy = devm_phy_create(dev, NULL, ufs_msm_phy_gen_ops, NULL);
generic_phy = devm_phy_create(dev, NULL, ufs_qcom_phy_gen_ops, NULL);
if (IS_ERR(generic_phy)) {
err = PTR_ERR(generic_phy);
dev_err(dev, "%s: failed to create phy %d\n", __func__, err);
@ -107,17 +108,17 @@ out:
/*
* This assumes the embedded phy structure inside generic_phy is of type
* struct ufs_msm_phy. In order to function properly it's crucial
* to keep the embedded struct "struct ufs_msm_phy common_cfg"
* struct ufs_qcom_phy. In order to function properly it's crucial
* to keep the embedded struct "struct ufs_qcom_phy common_cfg"
* as the first inside generic_phy.
*/
struct ufs_msm_phy *get_ufs_msm_phy(struct phy *generic_phy)
struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy)
{
return (struct ufs_msm_phy *)phy_get_drvdata(generic_phy);
return (struct ufs_qcom_phy *)phy_get_drvdata(generic_phy);
}
int ufs_msm_phy_base_init(struct platform_device *pdev,
struct ufs_msm_phy *phy_common)
int ufs_qcom_phy_base_init(struct platform_device *pdev,
struct ufs_qcom_phy *phy_common)
{
struct device *dev = &pdev->dev;
struct resource *res;
@ -141,13 +142,13 @@ out:
return err;
}
int ufs_msm_phy_clk_get(struct phy *phy,
const char *name, struct clk **clk_out)
int ufs_qcom_phy_clk_get(struct phy *phy,
const char *name, struct clk **clk_out)
{
struct clk *clk;
int err = 0;
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(phy);
struct device *dev = ufs_msm_phy->dev;
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
struct device *dev = ufs_qcom_phy->dev;
clk = devm_clk_get(dev, name);
if (IS_ERR(clk)) {
@ -161,60 +162,61 @@ int ufs_msm_phy_clk_get(struct phy *phy,
}
int
ufs_msm_phy_init_clks(struct phy *generic_phy, struct ufs_msm_phy *phy_common)
ufs_qcom_phy_init_clks(struct phy *generic_phy,
struct ufs_qcom_phy *phy_common)
{
int err;
err = ufs_msm_phy_clk_get(generic_phy, "tx_iface_clk",
&phy_common->tx_iface_clk);
err = ufs_qcom_phy_clk_get(generic_phy, "tx_iface_clk",
&phy_common->tx_iface_clk);
if (err)
goto out;
err = ufs_msm_phy_clk_get(generic_phy, "rx_iface_clk",
&phy_common->rx_iface_clk);
err = ufs_qcom_phy_clk_get(generic_phy, "rx_iface_clk",
&phy_common->rx_iface_clk);
if (err)
goto out;
err = ufs_msm_phy_clk_get(generic_phy, "ref_clk_src",
&phy_common->ref_clk_src);
err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk_src",
&phy_common->ref_clk_src);
if (err)
goto out;
err = ufs_msm_phy_clk_get(generic_phy, "ref_clk_parent",
&phy_common->ref_clk_parent);
err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk_parent",
&phy_common->ref_clk_parent);
if (err)
goto out;
err = ufs_msm_phy_clk_get(generic_phy, "ref_clk",
&phy_common->ref_clk);
err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk",
&phy_common->ref_clk);
out:
return err;
}
int
ufs_msm_phy_init_vregulators(struct phy *generic_phy,
struct ufs_msm_phy *phy_common)
ufs_qcom_phy_init_vregulators(struct phy *generic_phy,
struct ufs_qcom_phy *phy_common)
{
int err;
err = ufs_msm_phy_init_vreg(generic_phy, &phy_common->vdda_pll,
err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_pll,
"vdda-pll");
if (err)
goto out;
err = ufs_msm_phy_init_vreg(generic_phy, &phy_common->vdda_phy,
err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_phy,
"vdda-phy");
out:
return err;
}
int ufs_msm_phy_init_vreg(struct phy *phy,
struct ufs_msm_phy_vreg *vreg, const char *name)
int ufs_qcom_phy_init_vreg(struct phy *phy,
struct ufs_qcom_phy_vreg *vreg, const char *name)
{
int err = 0;
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(phy);
struct device *dev = ufs_msm_phy->dev;
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
struct device *dev = ufs_qcom_phy->dev;
char prop_name[MAX_PROP_NAME];
@ -263,16 +265,16 @@ out:
return err;
}
int ufs_msm_phy_cfg_vreg(struct phy *phy,
struct ufs_msm_phy_vreg *vreg, bool on)
int ufs_qcom_phy_cfg_vreg(struct phy *phy,
struct ufs_qcom_phy_vreg *vreg, bool on)
{
int ret = 0;
struct regulator *reg = vreg->reg;
const char *name = vreg->name;
int min_uV;
int uA_load;
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(phy);
struct device *dev = ufs_msm_phy->dev;
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
struct device *dev = ufs_qcom_phy->dev;
BUG_ON(!vreg);
@ -302,20 +304,20 @@ out:
return ret;
}
int ufs_msm_phy_enable_vreg(struct phy *phy,
struct ufs_msm_phy_vreg *vreg)
int ufs_qcom_phy_enable_vreg(struct phy *phy,
struct ufs_qcom_phy_vreg *vreg)
{
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(phy);
struct device *dev = ufs_msm_phy->dev;
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
struct device *dev = ufs_qcom_phy->dev;
int ret = 0;
if (!vreg || vreg->enabled)
goto out;
ret = ufs_msm_phy_cfg_vreg(phy, vreg, true);
ret = ufs_qcom_phy_cfg_vreg(phy, vreg, true);
if (ret) {
dev_err(dev, "%s: ufs_msm_phy_cfg_vreg() failed, err=%d\n",
__func__, ret);
dev_err(dev, "%s: ufs_qcom_phy_cfg_vreg() failed, err=%d\n",
__func__, ret);
goto out;
}
@ -331,10 +333,11 @@ out:
return ret;
}
int ufs_msm_phy_enable_ref_clk(struct phy *generic_phy)
int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy)
{
int ret = 0;
struct ufs_msm_phy *phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
if (phy->is_ref_clk_enabled)
goto out;
@ -374,11 +377,11 @@ out:
return ret;
}
int ufs_msm_phy_disable_vreg(struct phy *phy,
struct ufs_msm_phy_vreg *vreg)
int ufs_qcom_phy_disable_vreg(struct phy *phy,
struct ufs_qcom_phy_vreg *vreg)
{
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(phy);
struct device *dev = ufs_msm_phy->dev;
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
struct device *dev = ufs_qcom_phy->dev;
int ret = 0;
if (!vreg || !vreg->enabled)
@ -388,7 +391,7 @@ int ufs_msm_phy_disable_vreg(struct phy *phy,
if (!ret) {
/* ignore errors on applying disable config */
ufs_msm_phy_cfg_vreg(phy, vreg, false);
ufs_qcom_phy_cfg_vreg(phy, vreg, false);
vreg->enabled = false;
} else {
dev_err(dev, "%s: %s disable failed, err=%d\n",
@ -398,9 +401,9 @@ out:
return ret;
}
void ufs_msm_phy_disable_ref_clk(struct phy *generic_phy)
void ufs_qcom_phy_disable_ref_clk(struct phy *generic_phy)
{
struct ufs_msm_phy *phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
if (phy->is_ref_clk_enabled) {
clk_disable_unprepare(phy->ref_clk);
@ -410,14 +413,14 @@ void ufs_msm_phy_disable_ref_clk(struct phy *generic_phy)
}
}
void ufs_msm_phy_restore_swi_regs(struct phy *generic_phy)
void ufs_qcom_phy_restore_swi_regs(struct phy *generic_phy)
{
int i;
struct ufs_msm_phy *phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
for (i = 0; i < phy->cached_regs_table_size; i++) {
struct ufs_msm_phy_calibration *table =
(struct ufs_msm_phy_calibration *)phy->cached_regs;
struct ufs_qcom_phy_calibration *table =
(struct ufs_qcom_phy_calibration *)phy->cached_regs;
writel_relaxed(table[i].cfg_value, phy->mmio +
table[i].reg_offset);
}
@ -427,10 +430,11 @@ void ufs_msm_phy_restore_swi_regs(struct phy *generic_phy)
}
/* Turn ON M-PHY RMMI interface clocks */
int ufs_msm_phy_enable_iface_clk(struct phy *generic_phy)
int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy)
{
struct ufs_msm_phy *phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
int ret = 0;
if (phy->is_iface_clk_enabled)
goto out;
@ -454,9 +458,9 @@ out:
}
/* Turn OFF M-PHY RMMI interface clocks */
void ufs_msm_phy_disable_iface_clk(struct phy *generic_phy)
void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy)
{
struct ufs_msm_phy *phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
if (phy->is_iface_clk_enabled) {
clk_disable_unprepare(phy->tx_iface_clk);
@ -465,150 +469,150 @@ void ufs_msm_phy_disable_iface_clk(struct phy *generic_phy)
}
}
int ufs_msm_phy_is_cfg_restore_quirk_enabled(struct phy *phy)
int ufs_qcom_phy_is_cfg_restore_quirk_enabled(struct phy *phy)
{
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(phy);
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
return ufs_msm_phy->quirks & MSM_UFS_PHY_QUIRK_CFG_RESTORE;
return ufs_qcom_phy->quirks & UFS_QCOM_PHY_QUIRK_CFG_RESTORE;
}
int ufs_msm_phy_start_serdes(struct phy *generic_phy)
int ufs_qcom_phy_start_serdes(struct phy *generic_phy)
{
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
int ret = 0;
if (!ufs_msm_phy->phy_spec_ops->start_serdes) {
dev_err(ufs_msm_phy->dev, "%s: start_serdes() callback is not supported\n",
if (!ufs_qcom_phy->phy_spec_ops->start_serdes) {
dev_err(ufs_qcom_phy->dev, "%s: start_serdes() callback is not supported\n",
__func__);
ret = -ENOTSUPP;
} else {
ufs_msm_phy->phy_spec_ops->start_serdes(ufs_msm_phy);
ufs_qcom_phy->phy_spec_ops->start_serdes(ufs_qcom_phy);
}
return ret;
}
int ufs_msm_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)
int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)
{
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
int ret = 0;
if (!ufs_msm_phy->phy_spec_ops->set_tx_lane_enable) {
dev_err(ufs_msm_phy->dev, "%s: set_tx_lane_enable() callback is not supported\n",
if (!ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable) {
dev_err(ufs_qcom_phy->dev, "%s: set_tx_lane_enable() callback is not supported\n",
__func__);
ret = -ENOTSUPP;
} else {
ufs_msm_phy->phy_spec_ops->set_tx_lane_enable(ufs_msm_phy,
tx_lanes);
ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable(ufs_qcom_phy,
tx_lanes);
}
return ret;
}
void ufs_msm_phy_save_controller_version(struct phy *generic_phy,
u8 major, u16 minor, u16 step)
void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,
u8 major, u16 minor, u16 step)
{
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
ufs_msm_phy->host_ctrl_rev_major = major;
ufs_msm_phy->host_ctrl_rev_minor = minor;
ufs_msm_phy->host_ctrl_rev_step = step;
ufs_qcom_phy->host_ctrl_rev_major = major;
ufs_qcom_phy->host_ctrl_rev_minor = minor;
ufs_qcom_phy->host_ctrl_rev_step = step;
}
int ufs_msm_phy_calibrate_phy(struct phy *generic_phy)
int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy)
{
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
int ret = 0;
if (!ufs_msm_phy->phy_spec_ops->calibrate_phy) {
dev_err(ufs_msm_phy->dev, "%s: calibrate_phy() callback is not supported\n",
if (!ufs_qcom_phy->phy_spec_ops->calibrate_phy) {
dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() callback is not supported\n",
__func__);
ret = -ENOTSUPP;
} else {
ret = ufs_msm_phy->phy_spec_ops->
calibrate_phy(ufs_msm_phy);
ret = ufs_qcom_phy->phy_spec_ops->
calibrate_phy(ufs_qcom_phy);
if (ret)
dev_err(ufs_msm_phy->dev, "%s: calibrate_phy() failed %d\n",
dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() failed %d\n",
__func__, ret);
}
return ret;
}
int ufs_msm_phy_remove(struct phy *generic_phy,
struct ufs_msm_phy *ufs_msm_phy)
int ufs_qcom_phy_remove(struct phy *generic_phy,
struct ufs_qcom_phy *ufs_qcom_phy)
{
phy_power_off(generic_phy);
kfree(ufs_msm_phy->vdda_pll.name);
kfree(ufs_msm_phy->vdda_phy.name);
kfree(ufs_qcom_phy->vdda_pll.name);
kfree(ufs_qcom_phy->vdda_phy.name);
return 0;
}
int ufs_msm_phy_exit(struct phy *generic_phy)
int ufs_qcom_phy_exit(struct phy *generic_phy)
{
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
if (ufs_msm_phy->is_powered_on)
if (ufs_qcom_phy->is_powered_on)
phy_power_off(generic_phy);
return 0;
}
int ufs_msm_phy_is_pcs_ready(struct phy *generic_phy)
int ufs_qcom_phy_is_pcs_ready(struct phy *generic_phy)
{
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
if (!ufs_msm_phy->phy_spec_ops->is_physical_coding_sublayer_ready) {
dev_err(ufs_msm_phy->dev, "%s: is_physical_coding_sublayer_ready() callback is not supported\n",
if (!ufs_qcom_phy->phy_spec_ops->is_physical_coding_sublayer_ready) {
dev_err(ufs_qcom_phy->dev, "%s: is_physical_coding_sublayer_ready() callback is not supported\n",
__func__);
return -ENOTSUPP;
}
return ufs_msm_phy->phy_spec_ops->
is_physical_coding_sublayer_ready(ufs_msm_phy);
return ufs_qcom_phy->phy_spec_ops->
is_physical_coding_sublayer_ready(ufs_qcom_phy);
}
int ufs_msm_phy_save_configuration(struct phy *generic_phy)
int ufs_qcom_phy_save_configuration(struct phy *generic_phy)
{
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
int ret = 0;
if (!ufs_msm_phy->phy_spec_ops->save_configuration) {
dev_err(ufs_msm_phy->dev, "%s: save_configuration() callback is not supported\n",
if (!ufs_qcom_phy->phy_spec_ops->save_configuration) {
dev_err(ufs_qcom_phy->dev, "%s: save_configuration() callback is not supported\n",
__func__);
ret = -ENOTSUPP;
} else {
ufs_msm_phy->phy_spec_ops->save_configuration(ufs_msm_phy);
ufs_qcom_phy->phy_spec_ops->save_configuration(ufs_qcom_phy);
}
return ret;
}
int ufs_msm_phy_restore_configuration(struct phy *generic_phy)
int ufs_qcom_phy_restore_configuration(struct phy *generic_phy)
{
struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
int ret = 0;
if (!ufs_msm_phy->phy_spec_ops->restore_configuration) {
dev_err(ufs_msm_phy->dev, "%s: restore_configuration() callback is not supported\n",
if (!ufs_qcom_phy->phy_spec_ops->restore_configuration) {
dev_err(ufs_qcom_phy->dev, "%s: restore_configuration() callback is not supported\n",
__func__);
ret = -ENOTSUPP;
} else {
ufs_msm_phy->phy_spec_ops->restore_configuration(ufs_msm_phy);
ufs_qcom_phy->phy_spec_ops->restore_configuration(ufs_qcom_phy);
}
return ret;
}
int ufs_msm_phy_power_on(struct phy *generic_phy)
int ufs_qcom_phy_power_on(struct phy *generic_phy)
{
struct ufs_msm_phy *phy_common = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
struct device *dev = phy_common->dev;
int err;
err = ufs_msm_phy_enable_vreg(generic_phy, &phy_common->vdda_phy);
err = ufs_qcom_phy_enable_vreg(generic_phy, &phy_common->vdda_phy);
if (err) {
dev_err(dev, "%s enable vdda_phy failed, err=%d\n",
__func__, err);
@ -618,14 +622,14 @@ int ufs_msm_phy_power_on(struct phy *generic_phy)
phy_common->phy_spec_ops->power_control(phy_common, true);
/* vdda_pll also enables ref clock LDOs so enable it first */
err = ufs_msm_phy_enable_vreg(generic_phy, &phy_common->vdda_pll);
err = ufs_qcom_phy_enable_vreg(generic_phy, &phy_common->vdda_pll);
if (err) {
dev_err(dev, "%s enable vdda_pll failed, err=%d\n",
__func__, err);
goto out_disable_phy;
}
err = ufs_msm_phy_enable_ref_clk(generic_phy);
err = ufs_qcom_phy_enable_ref_clk(generic_phy);
if (err) {
dev_err(dev, "%s enable phy ref clock failed, err=%d\n",
__func__, err);
@ -636,23 +640,23 @@ int ufs_msm_phy_power_on(struct phy *generic_phy)
goto out;
out_disable_pll:
ufs_msm_phy_disable_vreg(generic_phy, &phy_common->vdda_pll);
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_pll);
out_disable_phy:
ufs_msm_phy_disable_vreg(generic_phy, &phy_common->vdda_phy);
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_phy);
out:
return err;
}
int ufs_msm_phy_power_off(struct phy *generic_phy)
int ufs_qcom_phy_power_off(struct phy *generic_phy)
{
struct ufs_msm_phy *phy_common = get_ufs_msm_phy(generic_phy);
struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
phy_common->phy_spec_ops->power_control(phy_common, false);
ufs_msm_phy_disable_ref_clk(generic_phy);
ufs_qcom_phy_disable_ref_clk(generic_phy);
ufs_msm_phy_disable_vreg(generic_phy, &phy_common->vdda_pll);
ufs_msm_phy_disable_vreg(generic_phy, &phy_common->vdda_phy);
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_pll);
ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_phy);
phy_common->is_powered_on = false;
return 0;

130
drivers/scsi/ufs/ufs-msm-phy.h
View file

@ -12,8 +12,8 @@
*
*/
#ifndef UFS_MSM_PHY_H_
#define UFS_MSM_PHY_H_
#ifndef UFS_QCOM_PHY_H_
#define UFS_QCOM_PHY_H_
#include <linux/io.h>
#include <linux/kernel.h>
@ -30,25 +30,25 @@
#include "unipro.h"
#include "ufs-msm.h"
#define UFS_MSM_PHY_CAL_ENTRY(reg, val) \
#define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \
{ \
.reg_offset = reg, \
.cfg_value = val, \
}
#define UFS_MSM_PHY_NAME_LEN 30
#define UFS_QCOM_PHY_NAME_LEN 30
struct ufs_msm_phy_stored_attributes {
struct ufs_qcom_phy_stored_attributes {
u32 att;
u32 value;
};
struct ufs_msm_phy_calibration {
struct ufs_qcom_phy_calibration {
u32 reg_offset;
u32 cfg_value;
};
struct ufs_msm_phy {
struct ufs_qcom_phy {
struct list_head list;
struct device *dev;
void __iomem *mmio;
@ -59,8 +59,8 @@ struct ufs_msm_phy {
struct clk *ref_clk_parent;
struct clk *ref_clk;
bool is_ref_clk_enabled;
struct ufs_msm_phy_vreg vdda_pll;
struct ufs_msm_phy_vreg vdda_phy;
struct ufs_qcom_phy_vreg vdda_pll;
struct ufs_qcom_phy_vreg vdda_phy;
unsigned int quirks;
u8 host_ctrl_rev_major;
u16 host_ctrl_rev_minor;
@ -97,7 +97,7 @@ struct ufs_msm_phy {
* 6. Write back the values to the PHY RMMI Attributes
* 7. Wait for UFS_PHY_PCS_READY_STATUS[0] to be '1'
*/
#define MSM_UFS_PHY_QUIRK_CFG_RESTORE (1 << 0)
#define UFS_QCOM_PHY_QUIRK_CFG_RESTORE (1 << 0)
/*
* If UFS PHY power down is deasserted and power is restored to analog
@ -106,7 +106,7 @@ struct ufs_msm_phy {
* it to exit Hibern8. Disabling the rx_sigdet during power-up masks
* the glitch.
*/
#define MSM_UFS_PHY_DIS_SIGDET_BEFORE_PWR_COLLAPSE (1 << 1)
#define UFS_QCOM_PHY_DIS_SIGDET_BEFORE_PWR_COLLAPSE (1 << 1)
/*
* If UFS link is put into Hibern8 and if UFS PHY analog hardware is
@ -115,17 +115,17 @@ struct ufs_msm_phy {
* Enabling this quirk will help to solve above issue by doing
* custom PHY settings just before PHY analog power collapse.
*/
#define MSM_UFS_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE (1 << 2)
#define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE (1 << 2)
char name[UFS_MSM_PHY_NAME_LEN];
struct ufs_msm_phy_calibration *cached_regs;
char name[UFS_QCOM_PHY_NAME_LEN];
struct ufs_qcom_phy_calibration *cached_regs;
int cached_regs_table_size;
bool is_powered_on;
struct ufs_msm_phy_specific_ops *phy_spec_ops;
struct ufs_qcom_phy_specific_ops *phy_spec_ops;
};
/**
* struct ufs_msm_phy_specific_ops - set of pointers to functions which have a
* struct ufs_qcom_phy_specific_ops - set of pointers to functions which have a
* specific implementation per phy. Each UFS phy, should implement
* those functions according to its spec and requirements
* @calibrate_phy: pointer to a function that calibrate the phy
@ -138,58 +138,58 @@ struct ufs_msm_phy {
* @power_control: pointer to a function that controls analog rail of phy
* and writes to QSERDES_RX_SIGDET_CNTRL attribute
*/
struct ufs_msm_phy_specific_ops {
int (*calibrate_phy) (struct ufs_msm_phy *phy);
void (*start_serdes) (struct ufs_msm_phy *phy);
void (*save_configuration)(struct ufs_msm_phy *phy);
void (*restore_configuration)(struct ufs_msm_phy *phy);
int (*is_physical_coding_sublayer_ready) (struct ufs_msm_phy *phy);
void (*set_tx_lane_enable) (struct ufs_msm_phy *phy, u32 val);
void (*power_control) (struct ufs_msm_phy *phy, bool val);
struct ufs_qcom_phy_specific_ops {
int (*calibrate_phy) (struct ufs_qcom_phy *phy);
void (*start_serdes) (struct ufs_qcom_phy *phy);
void (*save_configuration)(struct ufs_qcom_phy *phy);
void (*restore_configuration)(struct ufs_qcom_phy *phy);
int (*is_physical_coding_sublayer_ready) (struct ufs_qcom_phy *phy);
void (*set_tx_lane_enable) (struct ufs_qcom_phy *phy, u32 val);
void (*power_control) (struct ufs_qcom_phy *phy, bool val);
};
int ufs_msm_phy_init_vreg(struct phy *phy,
struct ufs_msm_phy_vreg *vreg, const char *name);
int ufs_msm_phy_cfg_vreg(struct phy *phy,
struct ufs_msm_phy_vreg *vreg, bool on);
int ufs_msm_phy_enable_vreg(struct phy *phy,
struct ufs_msm_phy_vreg *vreg);
int ufs_msm_phy_disable_vreg(struct phy *phy,
struct ufs_msm_phy_vreg *vreg);
int ufs_msm_phy_enable_ref_clk(struct phy *phy);
void ufs_msm_phy_disable_ref_clk(struct phy *phy);
int ufs_msm_phy_enable_iface_clk(struct phy *phy);
void ufs_msm_phy_disable_iface_clk(struct phy *phy);
void ufs_msm_phy_restore_swi_regs(struct phy *phy);
int ufs_msm_phy_link_startup_post_change(struct phy *phy,
int ufs_qcom_phy_init_vreg(struct phy *phy,
struct ufs_qcom_phy_vreg *vreg, const char *name);
int ufs_qcom_phy_cfg_vreg(struct phy *phy,
struct ufs_qcom_phy_vreg *vreg, bool on);
int ufs_qcom_phy_enable_vreg(struct phy *phy,
struct ufs_qcom_phy_vreg *vreg);
int ufs_qcom_phy_disable_vreg(struct phy *phy,
struct ufs_qcom_phy_vreg *vreg);
int ufs_qcom_phy_enable_ref_clk(struct phy *phy);
void ufs_qcom_phy_disable_ref_clk(struct phy *phy);
int ufs_qcom_phy_enable_iface_clk(struct phy *phy);
void ufs_qcom_phy_disable_iface_clk(struct phy *phy);
void ufs_qcom_phy_restore_swi_regs(struct phy *phy);
int ufs_qcom_phy_link_startup_post_change(struct phy *phy,
struct ufs_hba *hba);
int ufs_msm_phy_base_init(struct platform_device *pdev,
struct ufs_msm_phy *ufs_msm_phy_ops);
int ufs_msm_phy_is_cfg_restore_quirk_enabled(struct phy *phy);
struct ufs_msm_phy *get_ufs_msm_phy(struct phy *generic_phy);
int ufs_msm_phy_start_serdes(struct phy *generic_phy);
int ufs_msm_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes);
int ufs_msm_phy_calibrate_phy(struct phy *generic_phy);
int ufs_msm_phy_is_pcs_ready(struct phy *generic_phy);
int ufs_msm_phy_save_configuration(struct phy *generic_phy);
int ufs_msm_phy_restore_configuration(struct phy *generic_phy);
void ufs_msm_phy_save_controller_version(struct phy *generic_phy,
int ufs_qcom_phy_base_init(struct platform_device *pdev,
struct ufs_qcom_phy *ufs_qcom_phy_ops);
int ufs_qcom_phy_is_cfg_restore_quirk_enabled(struct phy *phy);
struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy);
int ufs_qcom_phy_start_serdes(struct phy *generic_phy);
int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes);
int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy);
int ufs_qcom_phy_is_pcs_ready(struct phy *generic_phy);
int ufs_qcom_phy_save_configuration(struct phy *generic_phy);
int ufs_qcom_phy_restore_configuration(struct phy *generic_phy);
void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,
u8 major, u16 minor, u16 step);
int ufs_msm_phy_power_on(struct phy *generic_phy);
int ufs_msm_phy_power_off(struct phy *generic_phy);
int ufs_msm_phy_exit(struct phy *generic_phy);
int ufs_msm_phy_init_clks(struct phy *generic_phy,
struct ufs_msm_phy *phy_common);
int ufs_msm_phy_init_vregulators(struct phy *generic_phy,
struct ufs_msm_phy *phy_common);
int ufs_msm_phy_remove(struct phy *generic_phy,
struct ufs_msm_phy *ufs_msm_phy);
struct phy *ufs_msm_phy_generic_probe(struct platform_device *pdev,
struct ufs_msm_phy *common_cfg,
struct phy_ops *ufs_msm_phy_gen_ops,
struct ufs_msm_phy_specific_ops *phy_spec_ops);
int ufs_msm_phy_calibrate(struct ufs_msm_phy *ufs_msm_phy,
struct ufs_msm_phy_calibration *tbl_A, int tbl_size_A,
struct ufs_msm_phy_calibration *tbl_B, int tbl_size_B,
int ufs_qcom_phy_power_on(struct phy *generic_phy);
int ufs_qcom_phy_power_off(struct phy *generic_phy);
int ufs_qcom_phy_exit(struct phy *generic_phy);
int ufs_qcom_phy_init_clks(struct phy *generic_phy,
struct ufs_qcom_phy *phy_common);
int ufs_qcom_phy_init_vregulators(struct phy *generic_phy,
struct ufs_qcom_phy *phy_common);
int ufs_qcom_phy_remove(struct phy *generic_phy,
struct ufs_qcom_phy *ufs_qcom_phy);
struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
struct ufs_qcom_phy *common_cfg,
struct phy_ops *ufs_qcom_phy_gen_ops,
struct ufs_qcom_phy_specific_ops *phy_spec_ops);
int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A,
struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B,
int rate);
#endif

356
drivers/scsi/ufs/ufs-msm.c
View file

@ -28,13 +28,13 @@
#include "ufs-msm.h"
#include "ufs-msm-phy.h"
static int ufs_msm_get_speed_mode(struct ufs_pa_layer_attr *p, char *result);
static int ufs_msm_get_bus_vote(struct ufs_msm_host *host,
static int ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result);
static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
const char *speed_mode);
static int ufs_msm_set_bus_vote(struct ufs_msm_host *host, int vote);
static int ufs_msm_update_sec_cfg(struct ufs_hba *hba, bool restore_sec_cfg);
static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
static int ufs_qcom_update_sec_cfg(struct ufs_hba *hba, bool restore_sec_cfg);
static int ufs_msm_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
{
int err = 0;
@ -47,7 +47,7 @@ static int ufs_msm_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
return err;
}
static int ufs_msm_host_clk_get(struct device *dev,
static int ufs_qcom_host_clk_get(struct device *dev,
const char *name, struct clk **clk_out)
{
struct clk *clk;
@ -65,7 +65,7 @@ static int ufs_msm_host_clk_get(struct device *dev,
return err;
}
static int ufs_msm_host_clk_enable(struct device *dev,
static int ufs_qcom_host_clk_enable(struct device *dev,
const char *name, struct clk *clk)
{
int err = 0;
@ -77,7 +77,7 @@ static int ufs_msm_host_clk_enable(struct device *dev,
return err;
}
static void ufs_msm_disable_lane_clks(struct ufs_msm_host *host)
static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
{
if (!host->is_lane_clks_enabled)
return;
@ -90,7 +90,7 @@ static void ufs_msm_disable_lane_clks(struct ufs_msm_host *host)
host->is_lane_clks_enabled = false;
}
static int ufs_msm_enable_lane_clks(struct ufs_msm_host *host)
static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
{
int err = 0;
struct device *dev = host->hba->dev;
@ -98,22 +98,22 @@ static int ufs_msm_enable_lane_clks(struct ufs_msm_host *host)
if (host->is_lane_clks_enabled)
return 0;
err = ufs_msm_host_clk_enable(dev,
err = ufs_qcom_host_clk_enable(dev,
"rx_lane0_sync_clk", host->rx_l0_sync_clk);
if (err)
goto out;
err = ufs_msm_host_clk_enable(dev,
err = ufs_qcom_host_clk_enable(dev,
"rx_lane1_sync_clk", host->rx_l1_sync_clk);
if (err)
goto disable_rx_l0;
err = ufs_msm_host_clk_enable(dev,
err = ufs_qcom_host_clk_enable(dev,
"tx_lane0_sync_clk", host->tx_l0_sync_clk);
if (err)
goto disable_rx_l1;
err = ufs_msm_host_clk_enable(dev,
err = ufs_qcom_host_clk_enable(dev,
"tx_lane1_sync_clk", host->tx_l1_sync_clk);
if (err)
goto disable_tx_l0;
@ -131,53 +131,53 @@ out:
return err;
}
static int ufs_msm_init_lane_clks(struct ufs_msm_host *host)
static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
{
int err = 0;
struct device *dev = host->hba->dev;
err = ufs_msm_host_clk_get(dev,
err = ufs_qcom_host_clk_get(dev,
"rx_lane0_sync_clk", &host->rx_l0_sync_clk);
if (err)
goto out;
err = ufs_msm_host_clk_get(dev,
err = ufs_qcom_host_clk_get(dev,
"rx_lane1_sync_clk", &host->rx_l1_sync_clk);
if (err)
goto out;
err = ufs_msm_host_clk_get(dev,
err = ufs_qcom_host_clk_get(dev,
"tx_lane0_sync_clk", &host->tx_l0_sync_clk);
if (err)
goto out;
err = ufs_msm_host_clk_get(dev,
err = ufs_qcom_host_clk_get(dev,
"tx_lane1_sync_clk", &host->tx_l1_sync_clk);
out:
return err;
}
static int ufs_msm_link_startup_post_change(struct ufs_hba *hba)
static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
{
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
struct phy *phy = host->generic_phy;
u32 tx_lanes;
int err = 0;
err = ufs_msm_get_connected_tx_lanes(hba, &tx_lanes);
err = ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
if (err)
goto out;
err = ufs_msm_phy_set_tx_lane_enable(phy, tx_lanes);
err = ufs_qcom_phy_set_tx_lane_enable(phy, tx_lanes);
if (err)
dev_err(hba->dev, "%s: ufs_msm_phy_set_tx_lane_enable failed\n",
dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable failed\n",
__func__);
out:
return err;
}
static int ufs_msm_check_hibern8(struct ufs_hba *hba)
static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
{
int err;
u32 tx_fsm_val = 0;
@ -213,44 +213,44 @@ static int ufs_msm_check_hibern8(struct ufs_hba *hba)
return err;
}
static int ufs_msm_power_up_sequence(struct ufs_hba *hba)
static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
{
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
struct phy *phy = host->generic_phy;
int ret = 0;
u8 major;
u16 minor, step;
/* Assert PHY reset and apply PHY calibration values */
ufs_msm_assert_reset(hba);
ufs_qcom_assert_reset(hba);
/* provide 1ms delay to let the reset pulse propagate */
usleep_range(1000, 1100);
ufs_msm_get_controller_revision(hba, &major, &minor, &step);
ufs_msm_phy_save_controller_version(phy, major, minor, step);
ret = ufs_msm_phy_calibrate_phy(phy);
ufs_qcom_get_controller_revision(hba, &major, &minor, &step);
ufs_qcom_phy_save_controller_version(phy, major, minor, step);
ret = ufs_qcom_phy_calibrate_phy(phy);
if (ret) {
dev_err(hba->dev, "%s: ufs_msm_phy_calibrate_phy() failed, ret = %d\n",
dev_err(hba->dev, "%s: ufs_qcom_phy_calibrate_phy() failed, ret = %d\n",
__func__, ret);
goto out;
}
/* De-assert PHY reset and start serdes */
ufs_msm_deassert_reset(hba);
ufs_qcom_deassert_reset(hba);
/*
* after reset deassertion, phy will need all ref clocks,
* voltage, current to settle down before starting serdes.
*/
usleep_range(1000, 1100);
ret = ufs_msm_phy_start_serdes(phy);
ret = ufs_qcom_phy_start_serdes(phy);
if (ret) {
dev_err(hba->dev, "%s: ufs_msm_phy_start_serdes() failed, ret = %d\n",
dev_err(hba->dev, "%s: ufs_qcom_phy_start_serdes() failed, ret = %d\n",
__func__, ret);
goto out;
}
ret = ufs_msm_phy_is_pcs_ready(phy);
ret = ufs_qcom_phy_is_pcs_ready(phy);
if (ret)
dev_err(hba->dev, "%s: is_physical_coding_sublayer_ready() failed, ret = %d\n",
__func__, ret);
@ -259,24 +259,24 @@ out:
return ret;
}
static int ufs_msm_hce_enable_notify(struct ufs_hba *hba, bool status)
static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, bool status)
{
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
int err = 0;
switch (status) {
case PRE_CHANGE:
ufs_msm_power_up_sequence(hba);
ufs_qcom_power_up_sequence(hba);
/*
* The PHY PLL output is the source of tx/rx lane symbol
* clocks, hence, enable the lane clocks only after PHY
* is initialized.
*/
err = ufs_msm_enable_lane_clks(host);
err = ufs_qcom_enable_lane_clks(host);
break;
case POST_CHANGE:
/* check if UFS PHY moved from DISABLED to HIBERN8 */
err = ufs_msm_check_hibern8(hba);
err = ufs_qcom_check_hibern8(hba);
break;
default:
dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
@ -291,7 +291,7 @@ static int ufs_msm_hce_enable_notify(struct ufs_hba *hba, bool status)
* in case of a failure
*/
static unsigned long
ufs_msm_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate)
ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate)
{
struct ufs_clk_info *clki;
u32 core_clk_period_in_ns;
@ -392,17 +392,17 @@ out:
return core_clk_rate;
}
static int ufs_msm_link_startup_notify(struct ufs_hba *hba, bool status)
static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, bool status)
{
unsigned long core_clk_rate = 0;
u32 core_clk_cycles_per_100ms;
switch (status) {
case PRE_CHANGE:
core_clk_rate = ufs_msm_cfg_timers(hba, UFS_PWM_G1,
SLOWAUTO_MODE, 0);
core_clk_rate = ufs_qcom_cfg_timers(hba, UFS_PWM_G1,
SLOWAUTO_MODE, 0);
if (!core_clk_rate) {
dev_err(hba->dev, "%s: ufs_msm_cfg_timers() failed\n",
dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
__func__);
return -EINVAL;
}
@ -412,7 +412,7 @@ static int ufs_msm_link_startup_notify(struct ufs_hba *hba, bool status)
REG_UFS_PA_LINK_STARTUP_TIMER);
break;
case POST_CHANGE:
ufs_msm_link_startup_post_change(hba);
ufs_qcom_link_startup_post_change(hba);
break;
default:
break;
@ -421,19 +421,19 @@ static int ufs_msm_link_startup_notify(struct ufs_hba *hba, bool status)
return 0;
}
static int ufs_msm_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
{
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
struct phy *phy = host->generic_phy;
int ret = 0;
if (ufs_msm_is_link_off(hba)) {
if (ufs_qcom_is_link_off(hba)) {
/*
* Disable the tx/rx lane symbol clocks before PHY is
* powered down as the PLL source should be disabled
* after downstream clocks are disabled.
*/
ufs_msm_disable_lane_clks(host);
ufs_qcom_disable_lane_clks(host);
phy_power_off(phy);
goto out;
@ -443,12 +443,12 @@ static int ufs_msm_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
* If UniPro link is not active, PHY ref_clk, main PHY analog power
* rail and low noise analog power rail for PLL can be switched off.
*/
if (!ufs_msm_is_link_active(hba)) {
if (ufs_msm_phy_is_cfg_restore_quirk_enabled(phy) &&
ufs_msm_is_link_hibern8(hba)) {
ret = ufs_msm_phy_save_configuration(phy);
if (!ufs_qcom_is_link_active(hba)) {
if (ufs_qcom_phy_is_cfg_restore_quirk_enabled(phy) &&
ufs_qcom_is_link_hibern8(hba)) {
ret = ufs_qcom_phy_save_configuration(phy);
if (ret)
dev_err(hba->dev, "%s: failed ufs_msm_phy_save_configuration %d\n",
dev_err(hba->dev, "%s: failed ufs_qcom_phy_save_configuration %d\n",
__func__, ret);
}
phy_power_off(phy);
@ -458,24 +458,24 @@ out:
return ret;
}
static bool ufs_msm_is_phy_config_restore_required(struct ufs_hba *hba)
static bool ufs_qcom_is_phy_config_restore_required(struct ufs_hba *hba)
{
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
struct phy *phy = host->generic_phy;
return ufs_msm_phy_is_cfg_restore_quirk_enabled(phy)
return ufs_qcom_phy_is_cfg_restore_quirk_enabled(phy)
&& ufshcd_is_link_hibern8(hba)
&& hba->is_sys_suspended;
}
static int ufs_msm_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
{
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
struct phy *phy = host->generic_phy;
int err;
if (ufs_msm_is_phy_config_restore_required(hba)) {
ufs_msm_assert_reset(hba);
if (ufs_qcom_is_phy_config_restore_required(hba)) {
ufs_qcom_assert_reset(hba);
/* provide 1ms delay to let the reset pulse propagate */
usleep_range(1000, 1100);
}
@ -487,11 +487,11 @@ static int ufs_msm_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
goto out;
}
if (ufs_msm_is_phy_config_restore_required(hba)) {
ufs_msm_phy_restore_swi_regs(phy);
if (ufs_qcom_is_phy_config_restore_required(hba)) {
ufs_qcom_phy_restore_swi_regs(phy);
/* De-assert PHY reset and start serdes */
ufs_msm_deassert_reset(hba);
ufs_qcom_deassert_reset(hba);
/*
* after reset deassertion, phy will need all ref clocks,
@ -499,21 +499,21 @@ static int ufs_msm_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
*/
usleep_range(1000, 1100);
err = ufs_msm_phy_start_serdes(phy);
err = ufs_qcom_phy_start_serdes(phy);
if (err) {
dev_err(hba->dev, "%s: ufs_msm_phy_start_serdes() failed, err = %d\n",
dev_err(hba->dev, "%s: ufs_qcom_phy_start_serdes() failed, err = %d\n",
__func__, err);
goto out;
}
err = ufs_msm_phy_restore_configuration(phy);
err = ufs_qcom_phy_restore_configuration(phy);
if (err) {
dev_err(hba->dev, "%s: ufs_msm_phy_restore_configuration() failed, err = %d\n",
dev_err(hba->dev, "%s: ufs_qcom_phy_restore_configuration() failed, err = %d\n",
__func__, err);
goto out;
}
err = ufs_msm_phy_is_pcs_ready(phy);
err = ufs_qcom_phy_is_pcs_ready(phy);
if (err) {
dev_err(hba->dev, "%s: is_physical_coding_sublayer_ready() failed, err = %d\n",
__func__, err);
@ -526,7 +526,7 @@ out:
return err;
}
struct ufs_msm_dev_params {
struct ufs_qcom_dev_params {
u32 pwm_rx_gear; /* pwm rx gear to work in */
u32 pwm_tx_gear; /* pwm tx gear to work in */
u32 hs_rx_gear; /* hs rx gear to work in */
@ -597,17 +597,17 @@ static int map_unmap_pwr_mode(u32 mode, bool is_pwr_to_arr)
}
#define NUM_OF_SUPPORTED_MODES 5
static int get_pwr_dev_param(struct ufs_msm_dev_params *msm_param,
struct ufs_pa_layer_attr *dev_max,
struct ufs_pa_layer_attr *dev_req)
static int get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
struct ufs_pa_layer_attr *dev_max,
struct ufs_pa_layer_attr *dev_req)
{
int arr[NUM_OF_SUPPORTED_MODES] = {0};
int i;
int min_power;
int min_msm_gear;
int min_qcom_gear;
int min_dev_gear;
bool is_max_dev_hs;
bool is_max_msm_hs;
bool is_max_qcom_hs;
/**
* mapping the max. supported power mode of the device
@ -617,12 +617,12 @@ static int get_pwr_dev_param(struct ufs_msm_dev_params *msm_param,
arr[map_unmap_pwr_mode(dev_max->pwr_rx, true)]++;
arr[map_unmap_pwr_mode(dev_max->pwr_tx, true)]++;
if (msm_param->desired_working_mode == SLOW) {
arr[map_unmap_pwr_mode(msm_param->rx_pwr_pwm, true)]++;
arr[map_unmap_pwr_mode(msm_param->tx_pwr_pwm, true)]++;
if (qcom_param->desired_working_mode == SLOW) {
arr[map_unmap_pwr_mode(qcom_param->rx_pwr_pwm, true)]++;
arr[map_unmap_pwr_mode(qcom_param->tx_pwr_pwm, true)]++;
} else {
arr[map_unmap_pwr_mode(msm_param->rx_pwr_hs, true)]++;
arr[map_unmap_pwr_mode(msm_param->tx_pwr_hs, true)]++;
arr[map_unmap_pwr_mode(qcom_param->rx_pwr_hs, true)]++;
arr[map_unmap_pwr_mode(qcom_param->tx_pwr_hs, true)]++;
}
for (i = 0; i < NUM_OF_SUPPORTED_MODES; ++i) {
@ -646,8 +646,8 @@ static int get_pwr_dev_param(struct ufs_msm_dev_params *msm_param,
* between device capability and vendor preferences.
* the same decision will be made for rx.
*/
dev_req->lane_tx = min_t(u32, dev_max->lane_tx, msm_param->tx_lanes);
dev_req->lane_rx = min_t(u32, dev_max->lane_rx, msm_param->rx_lanes);
dev_req->lane_tx = min_t(u32, dev_max->lane_tx, qcom_param->tx_lanes);
dev_req->lane_rx = min_t(u32, dev_max->lane_rx, qcom_param->rx_lanes);
if (dev_max->pwr_rx == SLOW_MODE ||
dev_max->pwr_rx == SLOWAUTO_MODE)
@ -662,14 +662,14 @@ static int get_pwr_dev_param(struct ufs_msm_dev_params *msm_param,
* setting the desired gear to be the minimum according to the desired
* power mode
*/
if (msm_param->desired_working_mode == SLOW) {
is_max_msm_hs = false;
min_msm_gear = min_t(u32, msm_param->pwm_rx_gear,
msm_param->pwm_tx_gear);
if (qcom_param->desired_working_mode == SLOW) {
is_max_qcom_hs = false;
min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
qcom_param->pwm_tx_gear);
} else {
is_max_msm_hs = true;
min_msm_gear = min_t(u32, msm_param->hs_rx_gear,
msm_param->hs_tx_gear);
is_max_qcom_hs = true;
min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
qcom_param->hs_tx_gear);
}
/**
@ -680,34 +680,34 @@ static int get_pwr_dev_param(struct ufs_msm_dev_params *msm_param,
* what the gear, as he is the one that also decided previously what
* pwr the device will be configured to.
*/
if ((is_max_dev_hs && is_max_msm_hs) ||
(!is_max_dev_hs && !is_max_msm_hs)) {
if ((is_max_dev_hs && is_max_qcom_hs) ||
(!is_max_dev_hs && !is_max_qcom_hs)) {
dev_req->gear_rx = dev_req->gear_tx =
min_t(u32, min_dev_gear, min_msm_gear);
min_t(u32, min_dev_gear, min_qcom_gear);
} else if (!is_max_dev_hs) {
dev_req->gear_rx = dev_req->gear_tx = min_dev_gear;
} else {
dev_req->gear_rx = dev_req->gear_tx = min_msm_gear;
dev_req->gear_rx = dev_req->gear_tx = min_qcom_gear;
}
dev_req->hs_rate = msm_param->hs_rate;
dev_req->hs_rate = qcom_param->hs_rate;
return 0;
}
static int ufs_msm_update_bus_bw_vote(struct ufs_msm_host *host)
static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
{
int vote;
int err = 0;
char mode[BUS_VECTOR_NAME_LEN];
err = ufs_msm_get_speed_mode(&host->dev_req_params, mode);
err = ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
if (err)
goto out;
vote = ufs_msm_get_bus_vote(host, mode);
vote = ufs_qcom_get_bus_vote(host, mode);
if (vote >= 0)
err = ufs_msm_set_bus_vote(host, vote);
err = ufs_qcom_set_bus_vote(host, vote);
else
err = vote;
@ -719,15 +719,15 @@ out:
return err;
}
static int ufs_msm_pwr_change_notify(struct ufs_hba *hba,
bool status,
struct ufs_pa_layer_attr *dev_max_params,
struct ufs_pa_layer_attr *dev_req_params)
static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
bool status,
struct ufs_pa_layer_attr *dev_max_params,
struct ufs_pa_layer_attr *dev_req_params)
{
u32 val;
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
struct phy *phy = host->generic_phy;
struct ufs_msm_dev_params ufs_msm_cap;
struct ufs_qcom_dev_params ufs_qcom_cap;
int ret = 0;
int res = 0;
@ -739,21 +739,21 @@ static int ufs_msm_pwr_change_notify(struct ufs_hba *hba,
switch (status) {
case PRE_CHANGE:
ufs_msm_cap.tx_lanes = UFS_MSM_LIMIT_NUM_LANES_TX;
ufs_msm_cap.rx_lanes = UFS_MSM_LIMIT_NUM_LANES_RX;
ufs_msm_cap.hs_rx_gear = UFS_MSM_LIMIT_HSGEAR_RX;
ufs_msm_cap.hs_tx_gear = UFS_MSM_LIMIT_HSGEAR_TX;
ufs_msm_cap.pwm_rx_gear = UFS_MSM_LIMIT_PWMGEAR_RX;
ufs_msm_cap.pwm_tx_gear = UFS_MSM_LIMIT_PWMGEAR_TX;
ufs_msm_cap.rx_pwr_pwm = UFS_MSM_LIMIT_RX_PWR_PWM;
ufs_msm_cap.tx_pwr_pwm = UFS_MSM_LIMIT_TX_PWR_PWM;
ufs_msm_cap.rx_pwr_hs = UFS_MSM_LIMIT_RX_PWR_HS;
ufs_msm_cap.tx_pwr_hs = UFS_MSM_LIMIT_TX_PWR_HS;
ufs_msm_cap.hs_rate = UFS_MSM_LIMIT_HS_RATE;
ufs_msm_cap.desired_working_mode =
UFS_MSM_LIMIT_DESIRED_MODE;
ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
ufs_qcom_cap.desired_working_mode =
UFS_QCOM_LIMIT_DESIRED_MODE;
ret = get_pwr_dev_param(&ufs_msm_cap, dev_max_params,
ret = get_pwr_dev_param(&ufs_qcom_cap, dev_max_params,
dev_req_params);
if (ret) {
pr_err("%s: failed to determine capabilities\n",
@ -763,10 +763,10 @@ static int ufs_msm_pwr_change_notify(struct ufs_hba *hba,
break;
case POST_CHANGE:
if (!ufs_msm_cfg_timers(hba, dev_req_params->gear_rx,
if (!ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
dev_req_params->pwr_rx,
dev_req_params->hs_rate)) {
dev_err(hba->dev, "%s: ufs_msm_cfg_timers() failed\n",
dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
__func__);
/*
* we return error code at the end of the routine,
@ -777,9 +777,9 @@ static int ufs_msm_pwr_change_notify(struct ufs_hba *hba,
}
val = ~(MAX_U32 << dev_req_params->lane_tx);
res = ufs_msm_phy_set_tx_lane_enable(phy, val);
res = ufs_qcom_phy_set_tx_lane_enable(phy, val);
if (res) {
dev_err(hba->dev, "%s: ufs_msm_phy_set_tx_lane_enable() failed res = %d\n",
dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable() failed res = %d\n",
__func__, res);
ret = res;
}
@ -787,7 +787,7 @@ static int ufs_msm_pwr_change_notify(struct ufs_hba *hba,
/* cache the power mode parameters to use internally */
memcpy(&host->dev_req_params,
dev_req_params, sizeof(*dev_req_params));
ufs_msm_update_bus_bw_vote(host);
ufs_qcom_update_bus_bw_vote(host);
break;
default:
ret = -EINVAL;
@ -798,20 +798,20 @@ out:
}
/**
* ufs_msm_advertise_quirks - advertise the known MSM UFS controller quirks
* ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
* @hba: host controller instance
*
* MSM UFS host controller might have some non standard behaviours (quirks)
* QCOM UFS host controller might have some non standard behaviours (quirks)
* than what is specified by UFSHCI specification. Advertise all such
* quirks to standard UFS host controller driver so standard takes them into
* account.
*/
static void ufs_msm_advertise_quirks(struct ufs_hba *hba)
static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
{
u8 major;
u16 minor, step;
ufs_msm_get_controller_revision(hba, &major, &minor, &step);
ufs_qcom_get_controller_revision(hba, &major, &minor, &step);
if ((major == 0x1) && (minor == 0x001) && (step == 0x0001))
hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
@ -824,7 +824,7 @@ static void ufs_msm_advertise_quirks(struct ufs_hba *hba)
| UFSHCD_QUIRK_BROKEN_LCC);
}
static int ufs_msm_get_bus_vote(struct ufs_msm_host *host,
static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
const char *speed_mode)
{
struct device *dev = host->hba->dev;
@ -849,7 +849,7 @@ out:
return err;
}
static int ufs_msm_set_bus_vote(struct ufs_msm_host *host, int vote)
static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
{
int err = 0;
@ -870,7 +870,7 @@ out:
return err;
}
static int ufs_msm_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
static int ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
{
int err = 0;
int gear = max_t(u32, p->gear_rx, p->gear_tx);
@ -907,35 +907,35 @@ out:
static int ufs_msm_setup_clocks(struct ufs_hba *hba, bool on)
static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on)
{
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
int err;
int vote = 0;
/*
* In case ufs_msm_init() is not yet done, simply ignore.
* This ufs_msm_setup_clocks() shall be called from
* ufs_msm_init() after init is done.
* In case ufs_qcom_init() is not yet done, simply ignore.
* This ufs_qcom_setup_clocks() shall be called from
* ufs_qcom_init() after init is done.
*/
if (!host)
return 0;
if (on) {
err = ufs_msm_phy_enable_iface_clk(host->generic_phy);
err = ufs_qcom_phy_enable_iface_clk(host->generic_phy);
if (err)
goto out;
vote = host->bus_vote.saved_vote;
if (vote == host->bus_vote.min_bw_vote)
ufs_msm_update_bus_bw_vote(host);
ufs_qcom_update_bus_bw_vote(host);
} else {
/* M-PHY RMMI interface clocks can be turned off */
ufs_msm_phy_disable_iface_clk(host->generic_phy);
ufs_qcom_phy_disable_iface_clk(host->generic_phy);
vote = host->bus_vote.min_bw_vote;
}
err = ufs_msm_set_bus_vote(host, vote);
err = ufs_qcom_set_bus_vote(host, vote);
if (err)
dev_err(hba->dev, "%s: set bus vote failed %d\n",
__func__, err);
@ -949,7 +949,7 @@ show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct ufs_hba *hba = dev_get_drvdata(dev);
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
return snprintf(buf, PAGE_SIZE, "%u\n",
host->bus_vote.is_max_bw_needed);
@ -960,18 +960,18 @@ store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct ufs_hba *hba = dev_get_drvdata(dev);
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
uint32_t value;
if (!kstrtou32(buf, 0, &value)) {
host->bus_vote.is_max_bw_needed = !!value;
ufs_msm_update_bus_bw_vote(host);
ufs_qcom_update_bus_bw_vote(host);
}
return count;
}
static int ufs_msm_bus_register(struct ufs_msm_host *host)
static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
{
int err;
struct msm_bus_scale_pdata *bus_pdata;
@ -1002,8 +1002,8 @@ static int ufs_msm_bus_register(struct ufs_msm_host *host)
}
/* cache the vote index for minimum and maximum bandwidth */
host->bus_vote.min_bw_vote = ufs_msm_get_bus_vote(host, "MIN");
host->bus_vote.max_bw_vote = ufs_msm_get_bus_vote(host, "MAX");
host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
@ -1025,7 +1025,7 @@ static int get_android_boot_dev(char *str)
__setup("androidboot.bootdevice=", get_android_boot_dev);
/**
* ufs_msm_init - bind phy with controller
* ufs_qcom_init - bind phy with controller
* @hba: host controller instance
*
* Binds PHY with controller and powers up PHY enabling clocks
@ -1034,11 +1034,11 @@ __setup("androidboot.bootdevice=", get_android_boot_dev);
* Returns -EPROBE_DEFER if binding fails, returns negative error
* on phy power up failure and returns zero on success.
*/
static int ufs_msm_init(struct ufs_hba *hba)
static int ufs_qcom_init(struct ufs_hba *hba)
{
int err;
struct device *dev = hba->dev;
struct ufs_msm_host *host;
struct ufs_qcom_host *host;
if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
return -ENODEV;
@ -1046,7 +1046,7 @@ static int ufs_msm_init(struct ufs_hba *hba)
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
if (!host) {
err = -ENOMEM;
dev_err(dev, "%s: no memory for msm ufs host\n", __func__);
dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
goto out;
}
@ -1062,9 +1062,9 @@ static int ufs_msm_init(struct ufs_hba *hba)
hba->priv = (void *)host;
/* restore the secure configuration */
ufs_msm_update_sec_cfg(hba, true);
ufs_qcom_update_sec_cfg(hba, true);
err = ufs_msm_bus_register(host);
err = ufs_qcom_bus_register(host);
if (err)
goto out_host_free;
@ -1073,16 +1073,16 @@ static int ufs_msm_init(struct ufs_hba *hba)
if (err)
goto out_unregister_bus;
err = ufs_msm_init_lane_clks(host);
err = ufs_qcom_init_lane_clks(host);
if (err)
goto out_disable_phy;
ufs_msm_advertise_quirks(hba);
ufs_qcom_advertise_quirks(hba);
hba->caps |= UFSHCD_CAP_CLK_GATING |
UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
ufs_msm_setup_clocks(hba, true);
ufs_qcom_setup_clocks(hba, true);
goto out;
out_disable_phy:
@ -1097,28 +1097,28 @@ out:
return err;
}
static void ufs_msm_exit(struct ufs_hba *hba)
static void ufs_qcom_exit(struct ufs_hba *hba)
{
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
msm_bus_scale_unregister_client(host->bus_vote.client_handle);
ufs_msm_disable_lane_clks(host);
ufs_qcom_disable_lane_clks(host);
phy_power_off(host->generic_phy);
}
void ufs_msm_clk_scale_notify(struct ufs_hba *hba)
void ufs_qcom_clk_scale_notify(struct ufs_hba *hba)
{
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
if (!dev_req_params)
return;
ufs_msm_cfg_timers(hba, dev_req_params->gear_rx,
ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
dev_req_params->pwr_rx,
dev_req_params->hs_rate);
ufs_msm_update_bus_bw_vote(host);
ufs_qcom_update_bus_bw_vote(host);
}
/*
@ -1129,10 +1129,10 @@ void ufs_msm_clk_scale_notify(struct ufs_hba *hba)
* @restore_sec_cfg: Set "true" if secure configuration needs to be restored
* and set "false" when secure configuration is lost.
*/
static int ufs_msm_update_sec_cfg(struct ufs_hba *hba, bool restore_sec_cfg)
static int ufs_qcom_update_sec_cfg(struct ufs_hba *hba, bool restore_sec_cfg)
{
int ret = 0, scm_ret = 0;
struct ufs_msm_host *host = hba->priv;
struct ufs_qcom_host *host = hba->priv;
/* scm command buffer structrue */
struct msm_scm_cmd_buf {
@ -1184,22 +1184,22 @@ out:
}
/**
* struct ufs_hba_msm_vops - UFS MSM specific variant operations
* struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
*
* The variant operations configure the necessary controller and PHY
* handshake during initializaiton.
*/
const struct ufs_hba_variant_ops ufs_hba_msm_vops = {
.name = "msm",
.init = ufs_msm_init,
.exit = ufs_msm_exit,
.clk_scale_notify = ufs_msm_clk_scale_notify,
.setup_clocks = ufs_msm_setup_clocks,
.hce_enable_notify = ufs_msm_hce_enable_notify,
.link_startup_notify = ufs_msm_link_startup_notify,
.pwr_change_notify = ufs_msm_pwr_change_notify,
.suspend = ufs_msm_suspend,
.resume = ufs_msm_resume,
.update_sec_cfg = ufs_msm_update_sec_cfg,
const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
.name = "qcom",
.init = ufs_qcom_init,
.exit = ufs_qcom_exit,
.clk_scale_notify = ufs_qcom_clk_scale_notify,
.setup_clocks = ufs_qcom_setup_clocks,
.hce_enable_notify = ufs_qcom_hce_enable_notify,
.link_startup_notify = ufs_qcom_link_startup_notify,
.pwr_change_notify = ufs_qcom_pwr_change_notify,
.suspend = ufs_qcom_suspend,
.resume = ufs_qcom_resume,
.update_sec_cfg = ufs_qcom_update_sec_cfg,
};
EXPORT_SYMBOL(ufs_hba_msm_vops);
EXPORT_SYMBOL(ufs_hba_qcom_vops);

54
drivers/scsi/ufs/ufs-msm.h
View file

@ -11,8 +11,8 @@
*
*/
#ifndef UFS_MSM_H_
#define UFS_MSM_H_
#ifndef UFS_QCOM_H_
#define UFS_QCOM_H_
#include <linux/phy/phy.h>
@ -34,20 +34,20 @@
#define SLOW 1
#define FAST 2
#define UFS_MSM_LIMIT_NUM_LANES_RX 2
#define UFS_MSM_LIMIT_NUM_LANES_TX 2
#define UFS_MSM_LIMIT_HSGEAR_RX UFS_HS_G2
#define UFS_MSM_LIMIT_HSGEAR_TX UFS_HS_G2
#define UFS_MSM_LIMIT_PWMGEAR_RX UFS_PWM_G4
#define UFS_MSM_LIMIT_PWMGEAR_TX UFS_PWM_G4
#define UFS_MSM_LIMIT_RX_PWR_PWM SLOW_MODE
#define UFS_MSM_LIMIT_TX_PWR_PWM SLOW_MODE
#define UFS_MSM_LIMIT_RX_PWR_HS FAST_MODE
#define UFS_MSM_LIMIT_TX_PWR_HS FAST_MODE
#define UFS_MSM_LIMIT_HS_RATE PA_HS_MODE_A
#define UFS_MSM_LIMIT_DESIRED_MODE FAST
#define UFS_QCOM_LIMIT_NUM_LANES_RX 2
#define UFS_QCOM_LIMIT_NUM_LANES_TX 2
#define UFS_QCOM_LIMIT_HSGEAR_RX UFS_HS_G2
#define UFS_QCOM_LIMIT_HSGEAR_TX UFS_HS_G2
#define UFS_QCOM_LIMIT_PWMGEAR_RX UFS_PWM_G4
#define UFS_QCOM_LIMIT_PWMGEAR_TX UFS_PWM_G4
#define UFS_QCOM_LIMIT_RX_PWR_PWM SLOW_MODE
#define UFS_QCOM_LIMIT_TX_PWR_PWM SLOW_MODE
#define UFS_QCOM_LIMIT_RX_PWR_HS FAST_MODE
#define UFS_QCOM_LIMIT_TX_PWR_HS FAST_MODE
#define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_A
#define UFS_QCOM_LIMIT_DESIRED_MODE FAST
/* MSM UFS host controller vendor specific registers */
/* QCOM UFS host controller vendor specific registers */
enum {
REG_UFS_SYS1CLK_1US = 0xC0,
REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
@ -73,12 +73,12 @@ enum {
MASK_CLK_NS_REG = 0xFFFC00,
};
enum ufs_msm_phy_init_type {
enum ufs_qcom_phy_init_type {
UFS_PHY_INIT_FULL,
UFS_PHY_INIT_CFG_RESTORE,
};
struct ufs_msm_phy_vreg {
struct ufs_qcom_phy_vreg {
const char *name;
struct regulator *reg;
int max_uA;
@ -88,7 +88,7 @@ struct ufs_msm_phy_vreg {
};
static inline void
ufs_msm_get_controller_revision(struct ufs_hba *hba,
ufs_qcom_get_controller_revision(struct ufs_hba *hba,
u8 *major, u16 *minor, u16 *step)
{
u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
@ -98,21 +98,21 @@ ufs_msm_get_controller_revision(struct ufs_hba *hba,
*step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
};
static inline void ufs_msm_assert_reset(struct ufs_hba *hba)
static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
{
ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
mb();
}
static inline void ufs_msm_deassert_reset(struct ufs_hba *hba)
static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
{
ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
mb();
}
struct ufs_msm_bus_vote {
struct ufs_qcom_bus_vote {
uint32_t client_handle;
uint32_t curr_vote;
int min_bw_vote;
@ -122,10 +122,10 @@ struct ufs_msm_bus_vote {
struct device_attribute max_bus_bw;
};
struct ufs_msm_host {
struct ufs_qcom_host {
struct phy *generic_phy;
struct ufs_hba *hba;
struct ufs_msm_bus_vote bus_vote;
struct ufs_qcom_bus_vote bus_vote;
struct ufs_pa_layer_attr dev_req_params;
struct clk *rx_l0_sync_clk;
struct clk *tx_l0_sync_clk;
@ -135,9 +135,9 @@ struct ufs_msm_host {
bool sec_cfg_updated;
};
#define ufs_msm_is_link_off(hba) ufshcd_is_link_off(hba)
#define ufs_msm_is_link_active(hba) ufshcd_is_link_active(hba)
#define ufs_msm_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
#define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
#define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
#define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
enum {
MASK_SERDES_START = 0x1,
@ -154,4 +154,4 @@ enum {
#define VDDA_PLL_MIN_UV 1800000
#define VDDA_PLL_MAX_UV 1800000
#endif /* UFS_MSM_H_ */
#endif /* UFS_QCOM_H_ */

6
drivers/scsi/ufs/ufshcd.h
View file

@ -779,10 +779,10 @@ int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, u8 *buf,
u32 size, bool ascii);
/* variant specific ops structures */
#ifdef CONFIG_SCSI_UFS_MSM
extern const struct ufs_hba_variant_ops ufs_hba_msm_vops;
extern const struct ufs_hba_variant_ops ufs_hba_qcom_vops;
#else
static const struct ufs_hba_variant_ops ufs_hba_msm_vops = {
.name = "msm",
static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
.name = "qcom",
};
#endif