msm: camera: Decouple CSIPHY 3phase clocks
3phase clock is required in CPHY mode but not in DPHY mode. Decouple 3phase clocks from other CSIPHY clocks in order to not enable 3phase clock when camera is in DPHY mode. Change-Id: I10f9a175ef937dab30afd9604cca3e870451b0c2 Signed-off-by: Xu Han <hanxu@codeaurora.org>
This commit is contained in:
Xu Han
David Keitel
parent
a69176361c
commit
8d9a297fc5
2 changed files with 46 additions and 13 deletions
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@ -517,6 +517,9 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev,
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if (csiphy_dev->csiphy_3phase == CSI_3PHASE_HW) {
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if (csiphy_params->csi_3phase == 1) {
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msm_cam_clk_enable(&csiphy_dev->pdev->dev,
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csiphy_dev->csiphy_3p_clk_info,
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csiphy_dev->csiphy_3p_clk, 2, 1);
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rc = msm_csiphy_3phase_lane_config(csiphy_dev,
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csiphy_params);
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csiphy_dev->num_irq_registers = 20;
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@ -1023,7 +1026,11 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg)
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msm_cam_clk_enable(&csiphy_dev->pdev->dev,
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csiphy_dev->csiphy_clk_info, csiphy_dev->csiphy_clk,
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csiphy_dev->num_clk, 0);
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iounmap(csiphy_dev->clk_mux_base);
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if (csiphy_dev->csiphy_3phase == CSI_3PHASE_HW)
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msm_cam_clk_enable(&csiphy_dev->pdev->dev,
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csiphy_dev->csiphy_3p_clk_info,
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csiphy_dev->csiphy_3p_clk, 2, 0);
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iounmap(csiphy_dev->clk_mux_base);
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}
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iounmap(csiphy_dev->base);
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csiphy_dev->base = NULL;
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@ -1131,7 +1138,11 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg)
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msm_cam_clk_enable(&csiphy_dev->pdev->dev,
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csiphy_dev->csiphy_clk_info, csiphy_dev->csiphy_clk,
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csiphy_dev->num_clk, 0);
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iounmap(csiphy_dev->clk_mux_base);
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if (csiphy_dev->csiphy_3phase == CSI_3PHASE_HW)
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msm_cam_clk_enable(&csiphy_dev->pdev->dev,
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csiphy_dev->csiphy_3p_clk_info,
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csiphy_dev->csiphy_3p_clk, 2, 0);
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iounmap(csiphy_dev->clk_mux_base);
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}
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iounmap(csiphy_dev->base);
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@ -1289,12 +1300,15 @@ static int msm_csiphy_get_clk_info(struct csiphy_device *csiphy_dev,
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uint32_t count;
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int i, rc;
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uint32_t rates[CSIPHY_NUM_CLK_MAX];
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const char *clk_name[CSIPHY_NUM_CLK_MAX];
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char *csi_3p_clk_name = "csi_phy_3p_clk";
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char *csi_3p_clk_src_name = "csiphy_3p_clk_src";
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uint32_t clk_cnt = 0;
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struct device_node *of_node;
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of_node = pdev->dev.of_node;
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count = of_property_count_strings(of_node, "clock-names");
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csiphy_dev->num_clk = count;
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CDBG("%s: count = %d\n", __func__, count);
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if (count == 0) {
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@ -1311,9 +1325,8 @@ static int msm_csiphy_get_clk_info(struct csiphy_device *csiphy_dev,
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for (i = 0; i < count; i++) {
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rc = of_property_read_string_index(of_node, "clock-names",
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i, &(csiphy_dev->csiphy_clk_info[i].clk_name));
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CDBG("%s: clock-names[%d] = %s\n", __func__,
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i, csiphy_dev->csiphy_clk_info[i].clk_name);
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i, &clk_name[i]);
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CDBG("%s: clock-names[%d] = %s\n", __func__, i, clk_name[i]);
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if (rc < 0) {
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pr_err("%s:%d, failed\n", __func__, __LINE__);
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return rc;
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@ -1326,18 +1339,37 @@ static int msm_csiphy_get_clk_info(struct csiphy_device *csiphy_dev,
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return rc;
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}
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for (i = 0; i < count; i++) {
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csiphy_dev->csiphy_clk_info[i].clk_rate = (rates[i] == 0) ?
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(long)-1 : rates[i];
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if (!strcmp(csiphy_dev->csiphy_clk_info[i].clk_name,
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if (!strcmp(clk_name[i], csi_3p_clk_src_name)) {
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csiphy_dev->csiphy_3p_clk_info[0].clk_name =
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clk_name[i];
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csiphy_dev->csiphy_3p_clk_info[0].clk_rate =
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(rates[i] == 0) ? (long)-1 : rates[i];
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continue;
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} else if (!strcmp(clk_name[i], csi_3p_clk_name)) {
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csiphy_dev->csiphy_3p_clk_info[1].clk_name =
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clk_name[i];
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csiphy_dev->csiphy_3p_clk_info[1].clk_rate =
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(rates[i] == 0) ? (long)-1 : rates[i];
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continue;
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}
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csiphy_dev->csiphy_clk_info[clk_cnt].clk_name =
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clk_name[i];
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csiphy_dev->csiphy_clk_info[clk_cnt].clk_rate =
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(rates[i] == 0) ? (long)-1 : rates[i];
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if (!strcmp(csiphy_dev->csiphy_clk_info[clk_cnt].clk_name,
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"csiphy_timer_src_clk")) {
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CDBG("%s:%d, copy csiphy_timer_src_clk",
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__func__, __LINE__);
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csiphy_dev->csiphy_max_clk = rates[i];
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csiphy_dev->csiphy_clk_index = i;
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csiphy_dev->csiphy_clk_index = clk_cnt;
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}
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CDBG("%s: clk_rate[%d] = %ld\n", __func__, i,
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csiphy_dev->csiphy_clk_info[i].clk_rate);
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CDBG("%s: clk_rate[%d] = %ld\n", __func__, clk_cnt,
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csiphy_dev->csiphy_clk_info[clk_cnt].clk_rate);
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clk_cnt++;
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}
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csiphy_dev->num_clk = clk_cnt;
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return 0;
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}
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@ -1371,7 +1403,6 @@ static int csiphy_probe(struct platform_device *pdev)
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CDBG("%s: device id = %d\n", __func__, pdev->id);
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}
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/* ToDo: Enable 3phase clock for dynamic clock enable/disable */
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rc = msm_csiphy_get_clk_info(new_csiphy_dev, pdev);
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if (rc < 0) {
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pr_err("%s: msm_csiphy_get_clk_info() failed", __func__);
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@ -155,6 +155,8 @@ struct csiphy_device {
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uint32_t num_clk;
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struct clk *csiphy_clk[CSIPHY_NUM_CLK_MAX];
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struct msm_cam_clk_info csiphy_clk_info[CSIPHY_NUM_CLK_MAX];
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struct clk *csiphy_3p_clk[2];
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struct msm_cam_clk_info csiphy_3p_clk_info[2];
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int32_t ref_count;
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uint16_t lane_mask[MAX_CSIPHY];
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uint32_t is_3_1_20nm_hw;
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