Merge "qcom-charger: qpnp-fg-gen3: add v2 SRAM register map"
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8dff1db3bc
2 changed files with 103 additions and 67 deletions
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@ -130,12 +130,13 @@ enum fg_sram_param_id {
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};
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struct fg_sram_param {
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u16 address;
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int offset;
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u16 addr_word;
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int addr_byte;
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u8 len;
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int value;
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int numrtr;
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int denmtr;
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int offset;
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void (*encode)(struct fg_sram_param *sp, enum fg_sram_param_id id,
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int val, u8 *buf);
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int (*decode)(struct fg_sram_param *sp, enum fg_sram_param_id id,
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@ -74,63 +74,113 @@
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#define LAST_MONOTONIC_SOC_WORD 119
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#define LAST_MONOTONIC_SOC_OFFSET 2
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/* v2 SRAM address and offset in ascending order */
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#define DELTA_SOC_THR_v2_WORD 13
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#define DELTA_SOC_THR_v2_OFFSET 0
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#define RECHARGE_SOC_THR_v2_WORD 14
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#define RECHARGE_SOC_THR_v2_OFFSET 1
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#define CHG_TERM_CURR_v2_WORD 15
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#define CHG_TERM_CURR_v2_OFFSET 1
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#define EMPTY_VOLT_v2_WORD 15
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#define EMPTY_VOLT_v2_OFFSET 2
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#define VBATT_LOW_v2_WORD 16
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#define VBATT_LOW_v2_OFFSET 0
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static int fg_decode_value_16b(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val);
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static int fg_decode_default(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val);
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static void fg_encode_voltage_16b(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val, u8 *buf);
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static void fg_encode_voltage_8b(struct fg_sram_param *sp,
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static void fg_encode_voltage(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val, u8 *buf);
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static void fg_encode_current(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val, u8 *buf);
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static void fg_encode_default(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val, u8 *buf);
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#define PARAM(_id, _addr, _offset, _len, _num, _den, _enc, _dec) \
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#define PARAM(_id, _addr_word, _addr_byte, _len, _num, _den, _offset, \
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_enc, _dec) \
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[FG_SRAM_##_id] = { \
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.address = _addr, \
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.offset = _offset, \
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.len = _len, \
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.numrtr = _num, \
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.denmtr = _den, \
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.encode = _enc, \
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.decode = _dec, \
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.addr_word = _addr_word, \
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.addr_byte = _addr_byte, \
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.len = _len, \
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.numrtr = _num, \
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.denmtr = _den, \
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.offset = _offset, \
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.encode = _enc, \
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.decode = _dec, \
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} \
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static struct fg_sram_param pmicobalt_v1_sram_params[] = {
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PARAM(BATT_SOC, BATT_SOC_WORD, BATT_SOC_OFFSET, 4, 1, 1, NULL,
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PARAM(BATT_SOC, BATT_SOC_WORD, BATT_SOC_OFFSET, 4, 1, 1, 0, NULL,
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fg_decode_default),
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PARAM(VOLTAGE_PRED, VOLTAGE_PRED_WORD, VOLTAGE_PRED_OFFSET, 2, 244141,
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1000, NULL, fg_decode_value_16b),
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PARAM(OCV, OCV_WORD, OCV_OFFSET, 2, 244141, 1000, NULL,
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1000, 0, NULL, fg_decode_value_16b),
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PARAM(OCV, OCV_WORD, OCV_OFFSET, 2, 244141, 1000, 0, NULL,
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fg_decode_value_16b),
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PARAM(RSLOW, RSLOW_WORD, RSLOW_OFFSET, 2, 244141, 1000, NULL,
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PARAM(RSLOW, RSLOW_WORD, RSLOW_OFFSET, 2, 244141, 1000, 0, NULL,
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fg_decode_value_16b),
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/* Entries below here are configurable during initialization */
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PARAM(CUTOFF_VOLT, CUTOFF_VOLT_WORD, CUTOFF_VOLT_OFFSET, 2, 1000000,
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244141, fg_encode_voltage_16b, NULL),
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244141, 0, fg_encode_voltage, NULL),
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PARAM(EMPTY_VOLT, EMPTY_VOLT_WORD, EMPTY_VOLT_OFFSET, 1, 100000, 390625,
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fg_encode_voltage_8b, NULL),
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-2500, fg_encode_voltage, NULL),
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PARAM(VBATT_LOW, VBATT_LOW_WORD, VBATT_LOW_OFFSET, 1, 100000, 390625,
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fg_encode_voltage_8b, NULL),
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-2500, fg_encode_voltage, NULL),
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PARAM(SYS_TERM_CURR, SYS_TERM_CURR_WORD, SYS_TERM_CURR_OFFSET, 3,
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1000000, 122070, fg_encode_current, NULL),
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1000000, 122070, 0, fg_encode_current, NULL),
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PARAM(CHG_TERM_CURR, CHG_TERM_CURR_WORD, CHG_TERM_CURR_OFFSET, 1,
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100000, 390625, fg_encode_current, NULL),
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100000, 390625, 0, fg_encode_current, NULL),
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PARAM(DELTA_SOC_THR, DELTA_SOC_THR_WORD, DELTA_SOC_THR_OFFSET, 1, 256,
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100, fg_encode_default, NULL),
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100, 0, fg_encode_default, NULL),
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PARAM(RECHARGE_SOC_THR, RECHARGE_SOC_THR_WORD, RECHARGE_SOC_THR_OFFSET,
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1, 256, 100, fg_encode_default, NULL),
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1, 256, 100, 0, fg_encode_default, NULL),
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PARAM(ESR_TIMER_DISCHG_MAX, ESR_TIMER_DISCHG_MAX_WORD,
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ESR_TIMER_DISCHG_MAX_OFFSET, 2, 1, 1, fg_encode_default, NULL),
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ESR_TIMER_DISCHG_MAX_OFFSET, 2, 1, 1, 0, fg_encode_default,
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NULL),
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PARAM(ESR_TIMER_DISCHG_INIT, ESR_TIMER_DISCHG_INIT_WORD,
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ESR_TIMER_DISCHG_INIT_OFFSET, 2, 1, 1, fg_encode_default,
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ESR_TIMER_DISCHG_INIT_OFFSET, 2, 1, 1, 0, fg_encode_default,
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NULL),
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PARAM(ESR_TIMER_CHG_MAX, ESR_TIMER_CHG_MAX_WORD,
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ESR_TIMER_CHG_MAX_OFFSET, 2, 1, 1, fg_encode_default, NULL),
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ESR_TIMER_CHG_MAX_OFFSET, 2, 1, 1, 0, fg_encode_default, NULL),
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PARAM(ESR_TIMER_CHG_INIT, ESR_TIMER_CHG_INIT_WORD,
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ESR_TIMER_CHG_INIT_OFFSET, 2, 1, 1, fg_encode_default, NULL),
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ESR_TIMER_CHG_INIT_OFFSET, 2, 1, 1, 0, fg_encode_default, NULL),
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};
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static struct fg_sram_param pmicobalt_v2_sram_params[] = {
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PARAM(BATT_SOC, BATT_SOC_WORD, BATT_SOC_OFFSET, 4, 1, 1, 0, NULL,
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fg_decode_default),
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PARAM(VOLTAGE_PRED, VOLTAGE_PRED_WORD, VOLTAGE_PRED_OFFSET, 2, 244141,
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1000, 0, NULL, fg_decode_value_16b),
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PARAM(OCV, OCV_WORD, OCV_OFFSET, 2, 244141, 1000, 0, NULL,
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fg_decode_value_16b),
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PARAM(RSLOW, RSLOW_WORD, RSLOW_OFFSET, 2, 244141, 1000, 0, NULL,
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fg_decode_value_16b),
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/* Entries below here are configurable during initialization */
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PARAM(CUTOFF_VOLT, CUTOFF_VOLT_WORD, CUTOFF_VOLT_OFFSET, 2, 1000000,
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244141, 0, fg_encode_voltage, NULL),
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PARAM(EMPTY_VOLT, EMPTY_VOLT_v2_WORD, EMPTY_VOLT_v2_OFFSET, 1, 100000,
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390625, -2000, fg_encode_voltage, NULL),
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PARAM(VBATT_LOW, VBATT_LOW_v2_WORD, VBATT_LOW_v2_OFFSET, 1, 100000,
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390625, -2000, fg_encode_voltage, NULL),
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PARAM(SYS_TERM_CURR, SYS_TERM_CURR_WORD, SYS_TERM_CURR_OFFSET, 3,
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1000000, 122070, 0, fg_encode_current, NULL),
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PARAM(CHG_TERM_CURR, CHG_TERM_CURR_v2_WORD, CHG_TERM_CURR_v2_OFFSET, 1,
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100000, 390625, 0, fg_encode_current, NULL),
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PARAM(DELTA_SOC_THR, DELTA_SOC_THR_v2_WORD, DELTA_SOC_THR_v2_OFFSET, 1,
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256, 100, 0, fg_encode_default, NULL),
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PARAM(RECHARGE_SOC_THR, RECHARGE_SOC_THR_v2_WORD,
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RECHARGE_SOC_THR_v2_OFFSET, 1, 256, 100, 0, fg_encode_default,
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NULL),
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PARAM(ESR_TIMER_DISCHG_MAX, ESR_TIMER_DISCHG_MAX_WORD,
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ESR_TIMER_DISCHG_MAX_OFFSET, 2, 1, 1, 0, fg_encode_default,
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NULL),
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PARAM(ESR_TIMER_DISCHG_INIT, ESR_TIMER_DISCHG_INIT_WORD,
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ESR_TIMER_DISCHG_INIT_OFFSET, 2, 1, 1, 0, fg_encode_default,
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NULL),
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PARAM(ESR_TIMER_CHG_MAX, ESR_TIMER_CHG_MAX_WORD,
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ESR_TIMER_CHG_MAX_OFFSET, 2, 1, 1, 0, fg_encode_default, NULL),
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PARAM(ESR_TIMER_CHG_INIT, ESR_TIMER_CHG_INIT_WORD,
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ESR_TIMER_CHG_INIT_OFFSET, 2, 1, 1, 0, fg_encode_default, NULL),
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};
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static int fg_gen3_debug_mask;
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@ -336,30 +386,13 @@ static int fg_decode(struct fg_sram_param *sp, enum fg_sram_param_id id,
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return sp[id].decode(sp, id, value);
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}
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static void fg_encode_voltage_16b(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val, u8 *buf)
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{
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int i, mask = 0xff;
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int64_t temp;
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temp = (int64_t)div_u64((u64)val * sp[id].numrtr, sp[id].denmtr);
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pr_debug("temp: %llx id: %d, val: %d, buf: [ ", temp, id, val);
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for (i = 0; i < sp[id].len; i++) {
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buf[i] = temp & mask;
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temp >>= 8;
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pr_debug("%x ", buf[i]);
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}
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pr_debug("]\n");
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}
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static void fg_encode_voltage_8b(struct fg_sram_param *sp,
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static void fg_encode_voltage(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val, u8 *buf)
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{
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int i, mask = 0xff;
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int64_t temp;
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/* Offset is 2.5V */
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val -= 2500;
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val += sp[id].offset;
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temp = (int64_t)div_u64((u64)val * sp[id].numrtr, sp[id].denmtr);
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pr_debug("temp: %llx id: %d, val: %d, buf: [ ", temp, id, val);
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for (i = 0; i < sp[id].len; i++) {
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@ -430,11 +463,11 @@ static int fg_get_sram_prop(struct fg_chip *chip, enum fg_sram_param_id id,
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if (id < 0 || id > FG_SRAM_MAX || chip->sp[id].len > sizeof(buf))
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return -EINVAL;
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rc = fg_sram_read(chip, chip->sp[id].address, chip->sp[id].offset,
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rc = fg_sram_read(chip, chip->sp[id].addr_word, chip->sp[id].addr_byte,
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buf, chip->sp[id].len, FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error reading address 0x%04x[%d] rc=%d\n",
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chip->sp[id].address, chip->sp[id].offset, rc);
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chip->sp[id].addr_word, chip->sp[id].addr_byte, rc);
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return rc;
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}
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@ -740,8 +773,8 @@ static int fg_set_esr_timer(struct fg_chip *chip, int cycles, bool charging,
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fg_encode(chip->sp, timer_max, cycles, buf);
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rc = fg_sram_write(chip,
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chip->sp[timer_max].address,
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chip->sp[timer_max].offset, buf,
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chip->sp[timer_max].addr_word,
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chip->sp[timer_max].addr_byte, buf,
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chip->sp[timer_max].len, flags);
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if (rc < 0) {
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pr_err("Error in writing esr_timer_dischg_max, rc=%d\n",
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@ -751,8 +784,8 @@ static int fg_set_esr_timer(struct fg_chip *chip, int cycles, bool charging,
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fg_encode(chip->sp, timer_init, cycles, buf);
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rc = fg_sram_write(chip,
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chip->sp[timer_init].address,
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chip->sp[timer_init].offset, buf,
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chip->sp[timer_init].addr_word,
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chip->sp[timer_init].addr_byte, buf,
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chip->sp[timer_init].len, flags);
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if (rc < 0) {
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pr_err("Error in writing esr_timer_dischg_init, rc=%d\n",
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@ -882,8 +915,8 @@ static int fg_hw_init(struct fg_chip *chip)
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u8 buf[4], val;
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fg_encode(chip->sp, FG_SRAM_CUTOFF_VOLT, chip->dt.cutoff_volt_mv, buf);
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_CUTOFF_VOLT].address,
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chip->sp[FG_SRAM_CUTOFF_VOLT].offset, buf,
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_CUTOFF_VOLT].addr_word,
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chip->sp[FG_SRAM_CUTOFF_VOLT].addr_byte, buf,
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chip->sp[FG_SRAM_CUTOFF_VOLT].len, FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error in writing cutoff_volt, rc=%d\n", rc);
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@ -891,8 +924,8 @@ static int fg_hw_init(struct fg_chip *chip)
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}
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fg_encode(chip->sp, FG_SRAM_EMPTY_VOLT, chip->dt.empty_volt_mv, buf);
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_EMPTY_VOLT].address,
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chip->sp[FG_SRAM_EMPTY_VOLT].offset, buf,
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_EMPTY_VOLT].addr_word,
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chip->sp[FG_SRAM_EMPTY_VOLT].addr_byte, buf,
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chip->sp[FG_SRAM_EMPTY_VOLT].len, FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error in writing empty_volt, rc=%d\n", rc);
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@ -901,8 +934,8 @@ static int fg_hw_init(struct fg_chip *chip)
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fg_encode(chip->sp, FG_SRAM_CHG_TERM_CURR, chip->dt.chg_term_curr_ma,
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buf);
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_CHG_TERM_CURR].address,
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chip->sp[FG_SRAM_CHG_TERM_CURR].offset, buf,
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_CHG_TERM_CURR].addr_word,
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chip->sp[FG_SRAM_CHG_TERM_CURR].addr_byte, buf,
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chip->sp[FG_SRAM_CHG_TERM_CURR].len, FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error in writing chg_term_curr, rc=%d\n", rc);
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@ -911,8 +944,8 @@ static int fg_hw_init(struct fg_chip *chip)
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fg_encode(chip->sp, FG_SRAM_SYS_TERM_CURR, chip->dt.sys_term_curr_ma,
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buf);
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_SYS_TERM_CURR].address,
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chip->sp[FG_SRAM_SYS_TERM_CURR].offset, buf,
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_SYS_TERM_CURR].addr_word,
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chip->sp[FG_SRAM_SYS_TERM_CURR].addr_byte, buf,
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chip->sp[FG_SRAM_SYS_TERM_CURR].len, FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error in writing sys_term_curr, rc=%d\n", rc);
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@ -922,8 +955,8 @@ static int fg_hw_init(struct fg_chip *chip)
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if (chip->dt.vbatt_low_thr_mv > 0) {
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fg_encode(chip->sp, FG_SRAM_VBATT_LOW,
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chip->dt.vbatt_low_thr_mv, buf);
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_VBATT_LOW].address,
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chip->sp[FG_SRAM_VBATT_LOW].offset, buf,
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_VBATT_LOW].addr_word,
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chip->sp[FG_SRAM_VBATT_LOW].addr_byte, buf,
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chip->sp[FG_SRAM_VBATT_LOW].len,
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FG_IMA_DEFAULT);
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if (rc < 0) {
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@ -936,8 +969,8 @@ static int fg_hw_init(struct fg_chip *chip)
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fg_encode(chip->sp, FG_SRAM_DELTA_SOC_THR,
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chip->dt.delta_soc_thr, buf);
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rc = fg_sram_write(chip,
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chip->sp[FG_SRAM_DELTA_SOC_THR].address,
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chip->sp[FG_SRAM_DELTA_SOC_THR].offset,
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chip->sp[FG_SRAM_DELTA_SOC_THR].addr_word,
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chip->sp[FG_SRAM_DELTA_SOC_THR].addr_byte,
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buf, chip->sp[FG_SRAM_DELTA_SOC_THR].len,
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FG_IMA_DEFAULT);
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if (rc < 0) {
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@ -950,8 +983,8 @@ static int fg_hw_init(struct fg_chip *chip)
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fg_encode(chip->sp, FG_SRAM_RECHARGE_SOC_THR,
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chip->dt.recharge_soc_thr, buf);
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rc = fg_sram_write(chip,
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chip->sp[FG_SRAM_RECHARGE_SOC_THR].address,
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chip->sp[FG_SRAM_RECHARGE_SOC_THR].offset,
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chip->sp[FG_SRAM_RECHARGE_SOC_THR].addr_word,
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chip->sp[FG_SRAM_RECHARGE_SOC_THR].addr_byte,
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buf, chip->sp[FG_SRAM_RECHARGE_SOC_THR].len,
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FG_IMA_DEFAULT);
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if (rc < 0) {
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@ -1283,6 +1316,8 @@ static int fg_parse_dt(struct fg_chip *chip)
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case PMICOBALT_SUBTYPE:
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if (chip->pmic_rev_id->rev4 < PMICOBALT_V2P0_REV4)
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chip->sp = pmicobalt_v1_sram_params;
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else if (chip->pmic_rev_id->rev4 == PMICOBALT_V2P0_REV4)
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chip->sp = pmicobalt_v2_sram_params;
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else
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return -EINVAL;
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break;
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