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ARM: virt: avoid clobbering lr when forcing svc mode

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The safe_svcmode_maskall macro is used to ensure that we are running in
svc mode, causing an exception return from hvc mode if required.

This patch removes the unneeded lr clobber from the macro and operates
entirely on the temporary parameter register instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[will: updated comment]
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Russell King 2012-12-03 15:39:43 +00:00 • committed by Will Deacon
parent 9931faca02
commit 8e9c24a2b2
1 changed files with 3 additions and 7 deletions
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10
arch/arm/include/asm/assembler.h
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@ -246,18 +246,14 @@
* *
* This macro is intended for forcing the CPU into SVC mode at boot time. * This macro is intended for forcing the CPU into SVC mode at boot time.
* you cannot return to the original mode. * you cannot return to the original mode.
*
* Beware, it also clobers LR.
*/ */
.macro safe_svcmode_maskall reg:req .macro safe_svcmode_maskall reg:req
#if __LINUX_ARM_ARCH__ >= 6 #if __LINUX_ARM_ARCH__ >= 6
mrs \reg , cpsr mrs \reg , cpsr
mov lr , \reg eor \reg, \reg, #HYP_MODE
and lr , lr , #MODE_MASK tst \reg, #MODE_MASK
cmp lr , #HYP_MODE
orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT
bic \reg , \reg , #MODE_MASK bic \reg , \reg , #MODE_MASK
orr \reg , \reg , #SVC_MODE orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
THUMB( orr \reg , \reg , #PSR_T_BIT ) THUMB( orr \reg , \reg , #PSR_T_BIT )
bne 1f bne 1f
orr \reg, \reg, #PSR_A_BIT orr \reg, \reg, #PSR_A_BIT