iommu/arm-smmu: Do an ATOS in the fault handler
In order to facilitate debugging of context faults, the result of a software table walk is currently printed as part of the fault handling. However, there are certain bugs and error conditions that can't be caught by doing a software table walk (like missing TLB invalidation or misbehaving hardware). Add a hardware table walk (via ATOS) to improve debugging capabilities. Change-Id: Ie89019df62f115627359e29b1f6cc5de3a36d1b5 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
This commit is contained in:
Mitchel Humpherys
David Keitel
parent
9f24ce3582
commit
8f418bc8a3
1 changed files with 104 additions and 11 deletions
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@ -943,9 +943,66 @@ static struct iommu_gather_ops arm_smmu_gather_ops = {
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.unprepare_pgtable = arm_smmu_unprepare_pgtable,
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};
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static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
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dma_addr_t iova);
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static phys_addr_t arm_smmu_iova_to_phys_hard_no_halt(
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struct iommu_domain *domain, dma_addr_t iova);
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static int arm_smmu_wait_for_halt(struct arm_smmu_device *smmu);
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static int arm_smmu_halt_nowait(struct arm_smmu_device *smmu);
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static void arm_smmu_resume(struct arm_smmu_device *smmu);
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static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
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dma_addr_t iova);
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static phys_addr_t arm_smmu_verify_fault(struct iommu_domain *domain,
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dma_addr_t iova, u32 fsr)
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{
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struct arm_smmu_domain *smmu_domain = domain->priv;
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struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
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struct arm_smmu_device *smmu;
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void __iomem *cb_base;
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u64 sctlr, sctlr_orig;
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phys_addr_t phys;
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smmu = smmu_domain->smmu;
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cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
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arm_smmu_halt_nowait(smmu);
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writel_relaxed(RESUME_TERMINATE, cb_base + ARM_SMMU_CB_RESUME);
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arm_smmu_wait_for_halt(smmu);
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/* clear FSR to allow ATOS to log any faults */
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writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
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/* disable stall mode momentarily */
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sctlr_orig = readl_relaxed(cb_base + ARM_SMMU_CB_SCTLR);
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sctlr = sctlr_orig & ~SCTLR_CFCFG;
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writel_relaxed(sctlr, cb_base + ARM_SMMU_CB_SCTLR);
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phys = arm_smmu_iova_to_phys_hard_no_halt(domain, iova);
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if (!phys) {
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dev_err(smmu->dev,
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"ATOS failed. Will issue a TLBIALL and try again...\n");
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arm_smmu_tlb_inv_context(smmu_domain);
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phys = arm_smmu_iova_to_phys_hard_no_halt(domain, iova);
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if (phys)
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dev_err(smmu->dev,
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"ATOS succeeded this time. Maybe we missed a TLB invalidation while messing with page tables earlier??\n");
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else
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dev_err(smmu->dev,
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"ATOS still failed. If the page tables look good (check the software table walk) then hardware might be misbehaving.\n");
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}
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/* restore SCTLR */
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writel_relaxed(sctlr_orig, cb_base + ARM_SMMU_CB_SCTLR);
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arm_smmu_resume(smmu);
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return phys;
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}
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static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
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{
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int flags, ret, tmp;
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@ -1016,6 +1073,9 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
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ret = IRQ_HANDLED;
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resume = ctx_hang_errata ? RESUME_TERMINATE : RESUME_RETRY;
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} else {
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phys_addr_t phys_atos = arm_smmu_verify_fault(domain, iova,
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fsr);
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dev_err(smmu->dev,
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"Unhandled context fault: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",
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iova, fsr, fsynr, cfg->cbndx);
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@ -1032,6 +1092,8 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
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(fsr & 0x80000000) ? "MULTI " : "");
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dev_err(smmu->dev,
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"soft iova-to-phys=%pa\n", &phys_soft);
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dev_err(smmu->dev,
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"hard iova-to-phys (ATOS)=%pa\n", &phys_atos);
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dev_err(smmu->dev, "SID=0x%x\n", frsynra & 0x1FF);
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ret = IRQ_NONE;
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resume = RESUME_TERMINATE;
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@ -1841,17 +1903,14 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
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return ret;
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}
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static int arm_smmu_halt(struct arm_smmu_device *smmu)
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static int arm_smmu_wait_for_halt(struct arm_smmu_device *smmu)
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{
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void __iomem *impl_def1_base = ARM_SMMU_IMPL_DEF1(smmu);
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u32 tmp;
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writel_relaxed(MICRO_MMU_CTRL_LOCAL_HALT_REQ,
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impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL);
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if (readl_poll_timeout_atomic(impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL,
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tmp, (tmp & MICRO_MMU_CTRL_IDLE),
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0, 30000)) {
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tmp, (tmp & MICRO_MMU_CTRL_IDLE),
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0, 30000)) {
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dev_err(smmu->dev, "Couldn't halt SMMU!\n");
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return -EBUSY;
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}
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@ -1859,6 +1918,26 @@ static int arm_smmu_halt(struct arm_smmu_device *smmu)
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return 0;
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}
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static int __arm_smmu_halt(struct arm_smmu_device *smmu, bool wait)
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{
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void __iomem *impl_def1_base = ARM_SMMU_IMPL_DEF1(smmu);
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writel_relaxed(MICRO_MMU_CTRL_LOCAL_HALT_REQ,
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impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL);
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return wait ? arm_smmu_wait_for_halt(smmu) : 0;
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}
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static int arm_smmu_halt(struct arm_smmu_device *smmu)
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{
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return __arm_smmu_halt(smmu, true);
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}
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static int arm_smmu_halt_nowait(struct arm_smmu_device *smmu)
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{
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return __arm_smmu_halt(smmu, false);
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}
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static void arm_smmu_resume(struct arm_smmu_device *smmu)
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{
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void __iomem *impl_def1_base = ARM_SMMU_IMPL_DEF1(smmu);
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@ -1869,8 +1948,8 @@ static void arm_smmu_resume(struct arm_smmu_device *smmu)
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writel_relaxed(reg, impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL);
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}
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static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
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dma_addr_t iova)
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static phys_addr_t __arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
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dma_addr_t iova, bool do_halt)
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{
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struct arm_smmu_domain *smmu_domain = domain->priv;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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@ -1887,7 +1966,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
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spin_lock_irqsave(&smmu->atos_lock, flags);
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if (arm_smmu_halt(smmu))
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if (do_halt && arm_smmu_halt(smmu))
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goto err_unlock;
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if (smmu->version == 1)
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@ -1905,7 +1984,8 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
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phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO);
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phys |= ((u64) readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32;
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arm_smmu_resume(smmu);
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if (do_halt)
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arm_smmu_resume(smmu);
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spin_unlock_irqrestore(&smmu->atos_lock, flags);
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if (phys & CB_PAR_F) {
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@ -1920,7 +2000,8 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
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return phys;
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err_resume:
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arm_smmu_resume(smmu);
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if (do_halt)
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arm_smmu_resume(smmu);
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err_unlock:
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spin_unlock_irqrestore(&smmu->atos_lock, flags);
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arm_smmu_disable_clocks(smmu);
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@ -1931,6 +2012,18 @@ err_unlock:
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return 0;
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}
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static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
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dma_addr_t iova)
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{
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return __arm_smmu_iova_to_phys_hard(domain, iova, true);
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}
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static phys_addr_t arm_smmu_iova_to_phys_hard_no_halt(
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struct iommu_domain *domain, dma_addr_t iova)
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{
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return __arm_smmu_iova_to_phys_hard(domain, iova, false);
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}
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static bool arm_smmu_capable(enum iommu_cap cap)
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{
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switch (cap) {
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