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drm/i915: Unify CHICKEN_PIPESL_1 register definitions

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We have two names for the same register CHICKEN_PIPESL_1 and
HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one.

Also rename the FBCQ disable bit to resemble the name we've
given to a similar bit on earlier platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2014-03-05 13:05:47 +02:00 • committed by Daniel Vetter
parent 2adb6db8d9
commit 8f670bb15a
2 changed files with 6 additions and 12 deletions
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10
drivers/gpu/drm/i915/i915_reg.h
View file

@ -1129,13 +1129,6 @@
#define FBC_REND_NUKE (1<<2) #define FBC_REND_NUKE (1<<2)
#define FBC_REND_CACHE_CLEAN (1<<1) #define FBC_REND_CACHE_CLEAN (1<<1)
#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0
#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4
#define HSW_BYPASS_FBC_QUEUE (1<<22)
#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \
_HSW_PIPE_SLICE_CHICKEN_1_A, + \
_HSW_PIPE_SLICE_CHICKEN_1_B)
/* /*
* GPIO regs * GPIO regs
*/ */
@ -4148,7 +4141,8 @@
#define _CHICKEN_PIPESL_1_A 0x420b0 #define _CHICKEN_PIPESL_1_A 0x420b0
#define _CHICKEN_PIPESL_1_B 0x420b4 #define _CHICKEN_PIPESL_1_B 0x420b4
#define DPRS_MASK_VBLANK_SRD (1 << 0) #define HSW_FBCQ_DIS (1 << 22)
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
#define DISP_ARB_CTL 0x45000 #define DISP_ARB_CTL 0x45000

8
drivers/gpu/drm/i915/intel_pm.c
View file

@ -299,9 +299,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
ILK_FBCQ_DIS); ILK_FBCQ_DIS);
} else { } else {
/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
I915_READ(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe)) | I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
HSW_BYPASS_FBC_QUEUE); HSW_FBCQ_DIS);
} }
I915_WRITE(SNB_DPFC_CTL_SA, I915_WRITE(SNB_DPFC_CTL_SA,
@ -4843,7 +4843,7 @@ static void gen8_init_clock_gating(struct drm_device *dev)
for_each_pipe(pipe) { for_each_pipe(pipe) {
I915_WRITE(CHICKEN_PIPESL_1(pipe), I915_WRITE(CHICKEN_PIPESL_1(pipe),
I915_READ(CHICKEN_PIPESL_1(pipe)) | I915_READ(CHICKEN_PIPESL_1(pipe)) |
DPRS_MASK_VBLANK_SRD); BDW_DPRS_MASK_VBLANK_SRD);
} }
/* Use Force Non-Coherent whenever executing a 3D context. This is a /* Use Force Non-Coherent whenever executing a 3D context. This is a