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[media] smiapp-pll: Constify limits argument to smiapp_pll_calculate()

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The limits are input parameters and should not be modified by the
smiapp_pll_calculate() function. Make them const.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Laurent Pinchart 2012-10-22 11:40:57 -03:00 • committed by Mauro Carvalho Chehab
parent 6ec84a28f5
commit 8f7e91a31f
2 changed files with 19 additions and 19 deletions
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33
drivers/media/i2c/smiapp-pll.c
View file

@ -88,7 +88,7 @@ static void print_pll(struct device *dev, struct smiapp_pll *pll)
} }
static int __smiapp_pll_calculate(struct device *dev, static int __smiapp_pll_calculate(struct device *dev,
struct smiapp_pll_limits *limits, const struct smiapp_pll_limits *limits,
struct smiapp_pll *pll, uint32_t mul, struct smiapp_pll *pll, uint32_t mul,
uint32_t div, uint32_t lane_op_clock_ratio) uint32_t div, uint32_t lane_op_clock_ratio)
{ {
@ -306,13 +306,9 @@ static int __smiapp_pll_calculate(struct device *dev,
pll->pixel_rate_csi = pll->pixel_rate_csi =
pll->op_pix_clk_freq_hz * lane_op_clock_ratio; pll->op_pix_clk_freq_hz * lane_op_clock_ratio;
rval = bounds_check(dev, pll->pre_pll_clk_div, rval = bounds_check(dev, pll->pll_ip_clk_freq_hz,
limits->min_pre_pll_clk_div, limits->min_pll_ip_freq_hz,
limits->max_pre_pll_clk_div, "pre_pll_clk_div"); limits->max_pll_ip_freq_hz,
if (!rval)
rval = bounds_check(
dev, pll->pll_ip_clk_freq_hz,
limits->min_pll_ip_freq_hz, limits->max_pll_ip_freq_hz,
"pll_ip_clk_freq_hz"); "pll_ip_clk_freq_hz");
if (!rval) if (!rval)
rval = bounds_check( rval = bounds_check(
@ -362,9 +358,12 @@ static int __smiapp_pll_calculate(struct device *dev,
return rval; return rval;
} }
int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits, int smiapp_pll_calculate(struct device *dev,
const struct smiapp_pll_limits *limits,
struct smiapp_pll *pll) struct smiapp_pll *pll)
{ {
uint16_t min_pre_pll_clk_div;
uint16_t max_pre_pll_clk_div;
uint32_t lane_op_clock_ratio; uint32_t lane_op_clock_ratio;
uint32_t mul, div; uint32_t mul, div;
unsigned int i; unsigned int i;
@ -397,33 +396,33 @@ int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits,
/* Figure out limits for pre-pll divider based on extclk */ /* Figure out limits for pre-pll divider based on extclk */
dev_dbg(dev, "min / max pre_pll_clk_div: %d / %d\n", dev_dbg(dev, "min / max pre_pll_clk_div: %d / %d\n",
limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div); limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
limits->max_pre_pll_clk_div = max_pre_pll_clk_div =
min_t(uint16_t, limits->max_pre_pll_clk_div, min_t(uint16_t, limits->max_pre_pll_clk_div,
clk_div_even(pll->ext_clk_freq_hz / clk_div_even(pll->ext_clk_freq_hz /
limits->min_pll_ip_freq_hz)); limits->min_pll_ip_freq_hz));
limits->min_pre_pll_clk_div = min_pre_pll_clk_div =
max_t(uint16_t, limits->min_pre_pll_clk_div, max_t(uint16_t, limits->min_pre_pll_clk_div,
clk_div_even_up( clk_div_even_up(
DIV_ROUND_UP(pll->ext_clk_freq_hz, DIV_ROUND_UP(pll->ext_clk_freq_hz,
limits->max_pll_ip_freq_hz))); limits->max_pll_ip_freq_hz)));
dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %d / %d\n", dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %d / %d\n",
limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div); min_pre_pll_clk_div, max_pre_pll_clk_div);
i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz); i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
mul = div_u64(pll->pll_op_clk_freq_hz, i); mul = div_u64(pll->pll_op_clk_freq_hz, i);
div = pll->ext_clk_freq_hz / i; div = pll->ext_clk_freq_hz / i;
dev_dbg(dev, "mul %d / div %d\n", mul, div); dev_dbg(dev, "mul %d / div %d\n", mul, div);
limits->min_pre_pll_clk_div = min_pre_pll_clk_div =
max_t(uint16_t, limits->min_pre_pll_clk_div, max_t(uint16_t, min_pre_pll_clk_div,
clk_div_even_up( clk_div_even_up(
DIV_ROUND_UP(mul * pll->ext_clk_freq_hz, DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
limits->max_pll_op_freq_hz))); limits->max_pll_op_freq_hz)));
dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %d / %d\n", dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %d / %d\n",
limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div); min_pre_pll_clk_div, max_pre_pll_clk_div);
for (pll->pre_pll_clk_div = limits->min_pre_pll_clk_div; for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
pll->pre_pll_clk_div <= limits->max_pre_pll_clk_div; pll->pre_pll_clk_div <= max_pre_pll_clk_div;
pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) { pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
rval = __smiapp_pll_calculate(dev, limits, pll, mul, div, rval = __smiapp_pll_calculate(dev, limits, pll, mul, div,
lane_op_clock_ratio); lane_op_clock_ratio);

3
drivers/media/i2c/smiapp-pll.h
View file

@ -107,7 +107,8 @@ struct smiapp_pll_limits {
struct device; struct device;
int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits, int smiapp_pll_calculate(struct device *dev,
const struct smiapp_pll_limits *limits,
struct smiapp_pll *pll); struct smiapp_pll *pll);
#endif /* SMIAPP_PLL_H */ #endif /* SMIAPP_PLL_H */