evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

drm/i915: Simplify CHV pipe A power well code

Browse source 
The pipe A power well is the "disp2d" well on CHV and pipe B and C wells
don't even exist. Thereforce we can remove the checks for pipe A vs.
others and just assume it's always pipe A.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2015-06-29 15:25:50 +03:00 • committed by Daniel Vetter
parent 60bfe44f83
commit 8fcd5cd8b3
1 changed files with 19 additions and 26 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
drivers/gpu/drm/i915/intel_runtime_pm.c
View file

@ -1042,19 +1042,18 @@ out:
static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well) struct i915_power_well *power_well)
{ {
WARN_ON_ONCE(power_well->data != PIPE_A);
chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
} }
static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well) struct i915_power_well *power_well)
{ {
WARN_ON_ONCE(power_well->data != PIPE_A && WARN_ON_ONCE(power_well->data != PIPE_A);
power_well->data != PIPE_B &&
power_well->data != PIPE_C);
chv_set_pipe_power_well(dev_priv, power_well, true); chv_set_pipe_power_well(dev_priv, power_well, true);
if (power_well->data == PIPE_A) {
spin_lock_irq(&dev_priv->irq_lock); spin_lock_irq(&dev_priv->irq_lock);
valleyview_enable_display_irqs(dev_priv); valleyview_enable_display_irqs(dev_priv);
spin_unlock_irq(&dev_priv->irq_lock); spin_unlock_irq(&dev_priv->irq_lock);
@ -1070,24 +1069,18 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
i915_redisable_vga_power_on(dev_priv->dev); i915_redisable_vga_power_on(dev_priv->dev);
} }
}
static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well) struct i915_power_well *power_well)
{ {
WARN_ON_ONCE(power_well->data != PIPE_A && WARN_ON_ONCE(power_well->data != PIPE_A);
power_well->data != PIPE_B &&
power_well->data != PIPE_C);
if (power_well->data == PIPE_A) {
spin_lock_irq(&dev_priv->irq_lock); spin_lock_irq(&dev_priv->irq_lock);
valleyview_disable_display_irqs(dev_priv); valleyview_disable_display_irqs(dev_priv);
spin_unlock_irq(&dev_priv->irq_lock); spin_unlock_irq(&dev_priv->irq_lock);
}
chv_set_pipe_power_well(dev_priv, power_well, false); chv_set_pipe_power_well(dev_priv, power_well, false);
if (power_well->data == PIPE_A)
vlv_power_sequencer_reset(dev_priv); vlv_power_sequencer_reset(dev_priv);
} }