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msm: mdss: Fix qseed3 clk calculation overflow

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Use u64 variables to store intermediate results while calculating
mdp clock for qseed3 scaling scenarios, using u32, results in overflow
and incorrect mdp clock setting.

Change-Id: I4fbc9aa1f30d36d35a9ad181185761e697cbbef7
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This commit is contained in:
Abhijit Kulkarni 2016-05-25 11:07:16 -07:00 • committed by Kyle Yan
parent 152fc477d3
commit 91785c5e5f
1 changed files with 8 additions and 8 deletions
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16
drivers/video/fbdev/msm/mdss_mdp_ctl.c
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@ -556,12 +556,12 @@ static u32 __calc_qseed3_mdp_clk_rate(struct mdss_mdp_pipe *pipe,
struct mdss_rect src, struct mdss_rect dst, u32 src_h,
u32 fps, u32 v_total)
{
u32 active_line_cycle, backfill_cycle, total_cycle;
u32 ver_dwnscale;
u32 active_line;
u32 backfill_line;
u64 active_line_cycle, backfill_cycle, total_cycle;
u64 ver_dwnscale;
u64 active_line;
u64 backfill_line;
ver_dwnscale = (src_h << PHASE_STEP_SHIFT) / dst.h;
ver_dwnscale = ((u64)src_h << PHASE_STEP_SHIFT) / dst.h;
if (ver_dwnscale > (MDSS_MDP_QSEED3_VER_DOWNSCALE_LIM
<< PHASE_STEP_SHIFT)) {
@ -584,12 +584,12 @@ static u32 __calc_qseed3_mdp_clk_rate(struct mdss_mdp_pipe *pipe,
total_cycle = active_line_cycle + backfill_cycle;
pr_debug("line: active=%d backfill=%d vds=%d\n",
pr_debug("line: active=%lld backfill=%lld vds=%lld\n",
active_line, backfill_line, ver_dwnscale);
pr_debug("cycle: total=%d active=%d backfill=%d\n",
pr_debug("cycle: total=%lld active=%lld backfill=%lld\n",
total_cycle, active_line_cycle, backfill_cycle);
return total_cycle * (fps * v_total);
return (u32)total_cycle * (fps * v_total);
}
static inline bool __is_vert_downscaling(u32 src_h,