evie/android_kernel_oneplus_msm8998
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mdss: DisplayPort: update link-training settings and do DP reset

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Add new settings for link-training parameters. Add
code in DP OFF to set the DP state to IDLE mode.

Add support for DP global reset before
initializing DP controller.

Change-Id: Ica893a9b56ae51b12f5d4a192b995aa966dc934e
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
This commit is contained in:
Chandan Uddaraju 2016-09-23 15:03:14 -07:00
parent a1b989e015
commit 92618b15ee
4 changed files with 23 additions and 10 deletions
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6
drivers/video/fbdev/msm/mdss_dp.c
View file

@ -1162,8 +1162,7 @@ int mdss_dp_off(struct mdss_panel_data *pdata)
mutex_lock(&dp_drv->train_mutex);
reinit_completion(&dp_drv->idle_comp);
mdss_dp_state_ctrl(&dp_drv->ctrl_io, 0);
mdss_dp_state_ctrl(&dp_drv->ctrl_io, ST_PUSH_IDLE);
if (dp_drv->link_clks_on)
mdss_dp_mainlink_ctrl(&dp_drv->ctrl_io, false);
@ -1305,9 +1304,10 @@ static int mdss_dp_host_init(struct mdss_panel_data *pdata)
mdss_dp_aux_init(dp_drv);
mdss_dp_phy_initialize(dp_drv);
mdss_dp_ctrl_reset(&dp_drv->ctrl_io);
mdss_dp_phy_reset(&dp_drv->ctrl_io);
mdss_dp_aux_reset(&dp_drv->ctrl_io);
mdss_dp_phy_initialize(dp_drv);
mdss_dp_aux_ctrl(&dp_drv->ctrl_io, true);
pr_debug("Ctrl_hw_rev =0x%x, phy hw_rev =0x%x\n",

14
drivers/video/fbdev/msm/mdss_dp_aux.c
View file

@ -1113,17 +1113,17 @@ static void dp_host_train_set(struct mdss_dp_drv_pdata *ep, int train)
}
char vm_pre_emphasis[4][4] = {
{0x00, 0x06, 0x09, 0x0C}, /* pe0, 0 db */
{0x00, 0x06, 0x09, 0xFF}, /* pe1, 3.5 db */
{0x03, 0x06, 0xFF, 0xFF}, /* pe2, 6.0 db */
{0x03, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
{0x00, 0x09, 0x11, 0x0C}, /* pe0, 0 db */
{0x00, 0x0A, 0x10, 0xFF}, /* pe1, 3.5 db */
{0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */
{0x00, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
};
/* voltage swing, 0.2v and 1.0v are not support */
char vm_voltage_swing[4][4] = {
{0x0a, 0x18, 0x1A, 0x1E}, /* sw0, 0.4v */
{0x07, 0x1A, 0x1E, 0xFF}, /* sw1, 0.6 v */
{0x1A, 0x1E, 0xFF, 0xFF}, /* sw1, 0.8 v */
{0x07, 0x0f, 0x12, 0x1E}, /* sw0, 0.4v */
{0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */
{0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */
{0x1E, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */
};

12
drivers/video/fbdev/msm/mdss_dp_util.c
View file

@ -143,6 +143,18 @@ void mdss_dp_aux_reset(struct dss_io_data *ctrl_io)
writel_relaxed(aux_ctrl, ctrl_io->base + DP_AUX_CTRL);
}
/* reset DP controller */
void mdss_dp_ctrl_reset(struct dss_io_data *ctrl_io)
{
u32 sw_reset = readl_relaxed(ctrl_io->base + DP_SW_RESET);
sw_reset |= BIT(0);
writel_relaxed(sw_reset, ctrl_io->base + DP_SW_RESET);
udelay(1000);
sw_reset &= ~BIT(0);
writel_relaxed(sw_reset, ctrl_io->base + DP_SW_RESET);
}
/* reset DP Mainlink */
void mdss_dp_mainlink_reset(struct dss_io_data *ctrl_io)
{

1
drivers/video/fbdev/msm/mdss_dp_util.h
View file

@ -207,6 +207,7 @@ int dp_aux_write(void *ep, struct edp_cmd *cmd);
void mdss_dp_state_ctrl(struct dss_io_data *ctrl_io, u32 data);
u32 mdss_dp_get_ctrl_hw_version(struct dss_io_data *ctrl_io);
u32 mdss_dp_get_phy_hw_version(struct dss_io_data *phy_io);
void mdss_dp_ctrl_reset(struct dss_io_data *ctrl_io);
void mdss_dp_aux_reset(struct dss_io_data *ctrl_io);
void mdss_dp_mainlink_reset(struct dss_io_data *ctrl_io);
void mdss_dp_phy_reset(struct dss_io_data *ctrl_io);