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phy: qcom-ufs-qmp-14nm: update rx min stall noconfig time

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Hibernate entry failures have been observed with some UFS devices.
The UFS PHY Rx termination is not disabled within the specified
RX_Min_STALL_NoConfig_Time_Capability of 15 SI.  The UFS device enables
mid-termination after RX_Min_STALL_NoConfig_Time_Capability SI.  The
combination of Rx terminated and device Tx mid-termination collapses
the line state to near the differential mid-point.  The signal detect
may report the line state incorrectly as DIF-P.  The incorrect DIF-P
moves the Rx FSM into the HS-Burst state rather than the intended
Hibern8 state.  Fix this issue by setting the UFS PHY's
RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY to 40.

Change-Id: I475e03686831e8131fd7ec1c30e6e8f53a6e188c
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This commit is contained in:
Subhash Jadavani 2015-11-19 11:06:05 -08:00 • committed by David Keitel
parent 415748c434
commit 927cc54089
1 changed files with 4 additions and 0 deletions
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4
drivers/phy/phy-qcom-ufs-qmp-14nm.h
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@ -88,6 +88,7 @@
#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x34)
#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x3C)
#define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP PHY_OFF(0xCC)
#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x138)
#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x148)
#define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x154)
@ -202,6 +203,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_0_0[] = {
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x12),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x06),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
/*
* UFS_PHY_RX_PWM_GEAR_BAND configuration is changed after the power up
@ -293,6 +295,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_1_0[] = {
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x12),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x06),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
};
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_2_0[] = {
@ -373,6 +376,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_2_0[] = {
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
};
static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {