mmc: sdhci-msm-ice: Enable ICE HCI if supported
Check if the SDHC has ICE HCI support. If support is present, enable the cryptoghrapic support inside SDHC. Also ensure that it is re-enabled after SDHC is reset. By default ICE HCI is disabled. Change-Id: I43a65279088d70b415c396bc3e51e0e510bb7f9c Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
This commit is contained in:
Veerabhadrarao Badiganti
parent
42e1251b38
commit
92907bcb94
4 changed files with 114 additions and 2 deletions
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@ -58,6 +58,52 @@ out:
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return ice_vops;
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}
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static
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void sdhci_msm_enable_ice_hci(struct sdhci_host *host, bool enable)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = pltfm_host->priv;
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u32 config = 0;
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u32 ice_cap = 0;
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/*
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* Enable the cryptographic support inside SDHC.
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* This is a global config which needs to be enabled
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* all the time.
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* Only when it it is enabled, the ICE_HCI capability
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* will get reflected in CQCAP register.
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*/
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config = readl_relaxed(host->ioaddr + HC_VENDOR_SPECIFIC_FUNC4);
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if (enable)
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config &= ~DISABLE_CRYPTO;
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else
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config |= DISABLE_CRYPTO;
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writel_relaxed(config, host->ioaddr + HC_VENDOR_SPECIFIC_FUNC4);
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/*
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* CQCAP register is in different register space from above
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* ice global enable register. So a mb() is required to ensure
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* above write gets completed before reading the CQCAP register.
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*/
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mb();
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/*
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* Check if ICE HCI capability support is present
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* If present, enable it.
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*/
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ice_cap = readl_relaxed(msm_host->cryptoio + ICE_CQ_CAPABILITIES);
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if (ice_cap & ICE_HCI_SUPPORT) {
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config = readl_relaxed(msm_host->cryptoio + ICE_CQ_CONFIG);
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if (enable)
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config |= CRYPTO_GENERAL_ENABLE;
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else
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config &= ~CRYPTO_GENERAL_ENABLE;
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writel_relaxed(config, msm_host->cryptoio + ICE_CQ_CONFIG);
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}
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}
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int sdhci_msm_ice_get_dev(struct sdhci_host *host)
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{
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struct device *sdhc_dev;
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@ -96,6 +142,37 @@ int sdhci_msm_ice_get_dev(struct sdhci_host *host)
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return 0;
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}
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static
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int sdhci_msm_ice_pltfm_init(struct sdhci_msm_host *msm_host)
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{
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struct resource *ice_memres = NULL;
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struct platform_device *pdev = msm_host->pdev;
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int err = 0;
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if (!msm_host->ice_hci_support)
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goto out;
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/*
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* ICE HCI registers are present in cmdq register space.
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* So map the cmdq mem for accessing ICE HCI registers.
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*/
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ice_memres = platform_get_resource_byname(pdev,
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IORESOURCE_MEM, "cmdq_mem");
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if (!ice_memres) {
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dev_err(&pdev->dev, "Failed to get iomem resource for ice\n");
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err = -EINVAL;
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goto out;
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}
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msm_host->cryptoio = devm_ioremap(&pdev->dev,
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ice_memres->start,
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resource_size(ice_memres));
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if (!msm_host->cryptoio) {
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dev_err(&pdev->dev, "Failed to remap registers\n");
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err = -ENOMEM;
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}
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out:
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return err;
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}
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int sdhci_msm_ice_init(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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@ -103,6 +180,13 @@ int sdhci_msm_ice_init(struct sdhci_host *host)
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int err = 0;
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if (msm_host->ice.vops->init) {
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err = sdhci_msm_ice_pltfm_init(msm_host);
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if (err)
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goto out;
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if (msm_host->ice_hci_support)
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sdhci_msm_enable_ice_hci(host, true);
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err = msm_host->ice.vops->init(msm_host->ice.pdev,
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msm_host,
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sdhci_msm_ice_error_cb);
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@ -110,6 +194,8 @@ int sdhci_msm_ice_init(struct sdhci_host *host)
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pr_err("%s: ice init err %d\n",
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mmc_hostname(host->mmc), err);
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sdhci_msm_ice_print_regs(host);
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if (msm_host->ice_hci_support)
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sdhci_msm_enable_ice_hci(host, false);
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goto out;
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}
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msm_host->ice.state = SDHCI_MSM_ICE_STATE_ACTIVE;
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@ -227,6 +313,10 @@ int sdhci_msm_ice_reset(struct sdhci_host *host)
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}
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}
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/* If ICE HCI support is present then re-enable it */
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if (msm_host->ice_hci_support)
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sdhci_msm_enable_ice_hci(host, true);
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if (msm_host->ice.state != SDHCI_MSM_ICE_STATE_ACTIVE) {
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pr_err("%s: ice is in invalid state after reset %d\n",
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mmc_hostname(host->mmc), msm_host->ice.state);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -37,6 +37,18 @@
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#define CORE_VENDOR_SPEC_ICE_CTRL_INFO_2_n 0x308
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#define CORE_VENDOR_SPEC_ICE_CTRL_INFO_3_n 0x30C
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/* ICE3.0 register which got added cmdq reg space */
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#define ICE_CQ_CAPABILITIES 0x04
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#define ICE_HCI_SUPPORT (1 << 28)
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#define ICE_CQ_CONFIG 0x08
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#define CRYPTO_GENERAL_ENABLE (1 << 1)
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/* ICE3.0 register which got added hc reg space */
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#define HC_VENDOR_SPECIFIC_FUNC4 0x260
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#define DISABLE_CRYPTO (1 << 15)
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#define HC_VENDOR_SPECIFIC_ICE_CTRL 0x800
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#define ICE_SW_RST_EN (1 << 0)
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/* SDHCI MSM ICE CTRL Info register offset */
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enum {
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OFFSET_SDHCI_MSM_ICE_CTRL_INFO_BYPASS = 0,
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@ -76,6 +88,11 @@ enum {
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SDHCI_MSM_ICE_STATE_SUSPENDED = 2,
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};
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/* crypto context fields in cmdq data command task descriptor */
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#define DATA_UNIT_NUM(x) (((u64)(x) & 0xFFFFFFFF) << 0)
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#define CRYPTO_CONFIG_INDEX(x) (((u64)(x) & 0xFF) << 32)
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#define CRYPTO_ENABLE(x) (((u64)(x) & 0x1) << 47)
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#ifdef CONFIG_MMC_SDHCI_MSM_ICE
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int sdhci_msm_ice_get_dev(struct sdhci_host *host);
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int sdhci_msm_ice_init(struct sdhci_host *host);
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@ -4099,6 +4099,9 @@ static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host,
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msm_host_offset->CORE_VENDOR_SPEC_CAPABILITIES0);
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/* keep track of the value in SDHCI_CAPABILITIES */
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msm_host->caps_0 = caps;
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if ((major == 1) && (minor >= 0x6b))
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msm_host->ice_hci_support = true;
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}
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#ifdef CONFIG_MMC_CQ_HCI
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -174,6 +174,8 @@ struct sdhci_msm_ice_data {
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struct sdhci_msm_host {
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struct platform_device *pdev;
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void __iomem *core_mem; /* MSM SDCC mapped address */
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void __iomem *cryptoio; /* ICE HCI mapped address */
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bool ice_hci_support;
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int pwr_irq; /* power irq */
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struct clk *clk; /* main SD/MMC bus clock */
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struct clk *pclk; /* SDHC peripheral bus clock */
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