regulator: spm-regulator: Add support for FTS426 type regulators
Add support for PMIC FTSMPS 426 type regulators. These have a 4 mV step size and a voltage control scheme consisting of two 8-bit registers defining a 16-bit voltage set point in units of millivolts. Also address the mode register configuration differences between FTSMPS 426 type regulators and other regulators supported in spm-regulator driver file. CRs-Fixed: 2037603 Change-Id: Ide54c8c9dd8113ab4588979ec97915403b3ecab1 Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
This commit is contained in:
Tirupathi Reddy
parent
a62f42964d
commit
94296ec070
1 changed files with 151 additions and 52 deletions
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@ -1,4 +1,4 @@
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/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -49,6 +49,7 @@ enum qpnp_regulator_uniq_type {
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QPNP_TYPE_HF,
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QPNP_TYPE_FTS2,
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QPNP_TYPE_FTS2p5,
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QPNP_TYPE_FTS426,
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QPNP_TYPE_ULT_HF,
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};
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@ -56,6 +57,7 @@ enum qpnp_regulator_type {
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QPNP_HF_TYPE = 0x03,
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QPNP_FTS2_TYPE = 0x1C,
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QPNP_FTS2p5_TYPE = 0x1C,
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QPNP_FTS426_TYPE = 0x1C,
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QPNP_ULT_HF_TYPE = 0x22,
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};
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@ -63,15 +65,22 @@ enum qpnp_regulator_subtype {
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QPNP_FTS2_SUBTYPE = 0x08,
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QPNP_HF_SUBTYPE = 0x08,
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QPNP_FTS2p5_SUBTYPE = 0x09,
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QPNP_FTS426_SUBTYPE = 0x0A,
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QPNP_ULT_HF_SUBTYPE = 0x0D,
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};
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enum qpnp_logical_mode {
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QPNP_LOGICAL_MODE_AUTO,
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QPNP_LOGICAL_MODE_PWM,
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};
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static const struct voltage_range fts2_range0 = {0, 350000, 1275000, 5000};
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static const struct voltage_range fts2_range1 = {0, 700000, 2040000, 10000};
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static const struct voltage_range fts2p5_range0
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= { 80000, 350000, 1355000, 5000};
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static const struct voltage_range fts2p5_range1
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= {160000, 700000, 2200000, 10000};
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static const struct voltage_range fts426_range = {0, 320000, 1352000, 4000};
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static const struct voltage_range ult_hf_range0 = {375000, 375000, 1562500,
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12500};
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static const struct voltage_range ult_hf_range1 = {750000, 750000, 1525000,
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@ -87,16 +96,27 @@ static const struct voltage_range hf_range1 = {1550000, 1550000, 3125000,
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#define QPNP_SMPS_REG_MODE 0x45
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#define QPNP_SMPS_REG_STEP_CTRL 0x61
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/* FTS426 voltage control registers */
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#define QPNP_FTS426_REG_VOLTAGE_LB 0x40
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#define QPNP_FTS426_REG_VOLTAGE_UB 0x41
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#define QPNP_FTS426_REG_VOLTAGE_VALID_LB 0x42
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#define QPNP_FTS426_REG_VOLTAGE_VALID_UB 0x43
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#define QPNP_SMPS_MODE_PWM 0x80
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#define QPNP_SMPS_MODE_AUTO 0x40
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#define QPNP_FTS426_MODE_PWM 0x07
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#define QPNP_FTS426_MODE_AUTO 0x06
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#define QPNP_SMPS_STEP_CTRL_STEP_MASK 0x18
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#define QPNP_SMPS_STEP_CTRL_STEP_SHIFT 3
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#define QPNP_SMPS_STEP_CTRL_DELAY_MASK 0x07
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#define QPNP_SMPS_STEP_CTRL_DELAY_SHIFT 0
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#define QPNP_FTS426_STEP_CTRL_DELAY_MASK 0x03
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#define QPNP_FTS426_STEP_CTRL_DELAY_SHIFT 0
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/* Clock rate in kHz of the FTS2 regulator reference clock. */
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#define QPNP_SMPS_CLOCK_RATE 19200
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#define QPNP_FTS426_CLOCK_RATE 4800
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/* Time to delay in us to ensure that a mode change has completed. */
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#define QPNP_FTS2_MODE_CHANGE_DELAY 50
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@ -107,6 +127,7 @@ static const struct voltage_range hf_range1 = {1550000, 1550000, 3125000,
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/* Minimum voltage stepper delay for each step. */
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#define QPNP_FTS2_STEP_DELAY 8
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#define QPNP_HF_STEP_DELAY 20
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#define QPNP_FTS426_STEP_DELAY 2
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/* Arbitrarily large max step size used to avoid possible numerical overflow */
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#define SPM_REGULATOR_MAX_STEP_UV 10000000
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@ -117,6 +138,8 @@ static const struct voltage_range hf_range1 = {1550000, 1550000, 3125000,
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*/
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#define QPNP_FTS2_STEP_MARGIN_NUM 4
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#define QPNP_FTS2_STEP_MARGIN_DEN 5
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#define QPNP_FTS426_STEP_MARGIN_NUM 10
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#define QPNP_FTS426_STEP_MARGIN_DEN 11
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/*
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* Settling delay for FTS2.5
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@ -140,8 +163,8 @@ struct spm_vreg {
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u32 max_step_uV;
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bool online;
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u16 spmi_base_addr;
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u8 init_mode;
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u8 mode;
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enum qpnp_logical_mode init_mode;
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enum qpnp_logical_mode mode;
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int step_rate;
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enum qpnp_regulator_uniq_type regulator_type;
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u32 cpu_num;
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@ -163,6 +186,9 @@ static int spm_regulator_uv_to_vlevel(struct spm_vreg *vreg, int uV)
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{
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int vlevel;
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if (vreg->regulator_type == QPNP_TYPE_FTS426)
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return roundup(uV, vreg->range->step_uV) / 1000;
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vlevel = DIV_ROUND_UP(uV - vreg->range->min_uV, vreg->range->step_uV);
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/* Fix VSET for ULT HF Buck */
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@ -177,6 +203,8 @@ static int spm_regulator_uv_to_vlevel(struct spm_vreg *vreg, int uV)
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static int spm_regulator_vlevel_to_uv(struct spm_vreg *vreg, int vlevel)
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{
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if (vreg->regulator_type == QPNP_TYPE_FTS426)
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return vlevel * 1000;
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/*
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* Calculate ULT HF buck VSET based on range:
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* In case of range 0: VSET is a 7 bit value.
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@ -204,32 +232,91 @@ static unsigned spm_regulator_vlevel_to_selector(struct spm_vreg *vreg,
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static int qpnp_smps_read_voltage(struct spm_vreg *vreg)
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{
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int rc;
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u8 reg = 0;
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uint val;
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u8 val[2] = {0};
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rc = regmap_read(vreg->regmap,
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vreg->spmi_base_addr + QPNP_SMPS_REG_VOLTAGE_SETPOINT,
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&val);
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if (rc) {
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dev_err(&vreg->pdev->dev,
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"%s: could not read voltage setpoint register, rc=%d\n",
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__func__, rc);
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return rc;
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if (vreg->regulator_type == QPNP_TYPE_FTS426) {
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rc = regmap_bulk_read(vreg->regmap,
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vreg->spmi_base_addr + QPNP_FTS426_REG_VOLTAGE_VALID_LB,
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val, 2);
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if (rc) {
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dev_err(&vreg->pdev->dev, "%s: could not read voltage setpoint registers, rc=%d\n",
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__func__, rc);
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return rc;
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}
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vreg->last_set_vlevel = ((unsigned)val[1] << 8) | val[0];
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} else {
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rc = regmap_bulk_read(vreg->regmap,
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vreg->spmi_base_addr + QPNP_SMPS_REG_VOLTAGE_SETPOINT,
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val, 1);
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if (rc) {
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dev_err(&vreg->pdev->dev, "%s: could not read voltage setpoint register, rc=%d\n",
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__func__, rc);
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return rc;
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}
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vreg->last_set_vlevel = val[0];
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}
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reg = (u8)val;
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vreg->last_set_vlevel = reg;
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vreg->last_set_uV = spm_regulator_vlevel_to_uv(vreg, reg);
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vreg->last_set_uV = spm_regulator_vlevel_to_uv(vreg,
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vreg->last_set_vlevel);
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return rc;
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}
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static int qpnp_smps_write_voltage(struct spm_vreg *vreg, unsigned vlevel)
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{
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int rc = 0;
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u8 reg[2];
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/* Set voltage control registers via SPMI. */
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reg[0] = vlevel & 0xFF;
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reg[1] = (vlevel >> 8) & 0xFF;
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if (vreg->regulator_type == QPNP_TYPE_FTS426) {
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rc = regmap_bulk_write(vreg->regmap,
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vreg->spmi_base_addr + QPNP_FTS426_REG_VOLTAGE_LB,
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reg, 2);
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} else {
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rc = regmap_write(vreg->regmap,
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vreg->spmi_base_addr + QPNP_SMPS_REG_VOLTAGE_SETPOINT,
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reg[0]);
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}
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if (rc)
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pr_err("%s: regmap_write failed, rc=%d\n",
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vreg->rdesc.name, rc);
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return rc;
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}
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static inline enum qpnp_logical_mode qpnp_regval_to_mode(struct spm_vreg *vreg,
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u8 regval)
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{
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if (vreg->regulator_type == QPNP_TYPE_FTS426)
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return (regval == QPNP_FTS426_MODE_PWM)
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? QPNP_LOGICAL_MODE_PWM : QPNP_LOGICAL_MODE_AUTO;
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else
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return (regval & QPNP_SMPS_MODE_PWM)
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? QPNP_LOGICAL_MODE_PWM : QPNP_LOGICAL_MODE_AUTO;
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}
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static inline u8 qpnp_mode_to_regval(struct spm_vreg *vreg,
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enum qpnp_logical_mode mode)
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{
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if (vreg->regulator_type == QPNP_TYPE_FTS426)
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return (mode == QPNP_LOGICAL_MODE_PWM)
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? QPNP_FTS426_MODE_PWM : QPNP_FTS426_MODE_AUTO;
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else
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return (mode == QPNP_LOGICAL_MODE_PWM)
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? QPNP_SMPS_MODE_PWM : QPNP_SMPS_MODE_AUTO;
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}
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static int qpnp_smps_set_mode(struct spm_vreg *vreg, u8 mode)
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{
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int rc;
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rc = regmap_write(vreg->regmap,
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vreg->spmi_base_addr + QPNP_SMPS_REG_MODE, mode);
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vreg->spmi_base_addr + QPNP_SMPS_REG_MODE,
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qpnp_mode_to_regval(vreg, mode));
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if (rc)
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dev_err(&vreg->pdev->dev,
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"%s: could not write to mode register, rc=%d\n",
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@ -275,7 +362,6 @@ static int spm_regulator_write_voltage(struct spm_vreg *vreg, int uV)
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bool spm_failed = false;
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int rc = 0;
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u32 slew_delay;
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u8 reg;
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if (likely(!vreg->bypass_spm)) {
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/* Set voltage control register via SPM. */
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@ -288,13 +374,9 @@ static int spm_regulator_write_voltage(struct spm_vreg *vreg, int uV)
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}
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if (unlikely(vreg->bypass_spm || spm_failed)) {
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/* Set voltage control register via SPMI. */
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reg = vlevel;
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rc = regmap_write(vreg->regmap,
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vreg->spmi_base_addr + QPNP_SMPS_REG_VOLTAGE_SETPOINT,
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reg);
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rc = qpnp_smps_write_voltage(vreg, vlevel);
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if (rc) {
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pr_err("%s: regmap_write failed, rc=%d\n",
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pr_err("%s: voltage write failed, rc=%d\n",
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vreg->rdesc.name, rc);
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return rc;
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}
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@ -351,12 +433,12 @@ static int _spm_regulator_set_voltage(struct regulator_dev *rdev)
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return 0;
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pwm_required = (vreg->regulator_type == QPNP_TYPE_FTS2)
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&& !(vreg->init_mode & QPNP_SMPS_MODE_PWM)
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&& (vreg->init_mode != QPNP_LOGICAL_MODE_PWM)
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&& vreg->uV > vreg->last_set_uV;
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if (pwm_required) {
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/* Switch to PWM mode so that voltage ramping is fast. */
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rc = qpnp_smps_set_mode(vreg, QPNP_SMPS_MODE_PWM);
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rc = qpnp_smps_set_mode(vreg, QPNP_LOGICAL_MODE_PWM);
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if (rc)
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return rc;
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}
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@ -375,7 +457,7 @@ static int _spm_regulator_set_voltage(struct regulator_dev *rdev)
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/* Wait for mode transition to complete. */
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udelay(QPNP_FTS2_MODE_CHANGE_DELAY - QPNP_SPMI_WRITE_MIN_DELAY);
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/* Switch to AUTO mode so that power consumption is lowered. */
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rc = qpnp_smps_set_mode(vreg, QPNP_SMPS_MODE_AUTO);
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rc = qpnp_smps_set_mode(vreg, QPNP_LOGICAL_MODE_AUTO);
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if (rc)
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return rc;
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}
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@ -466,7 +548,7 @@ static unsigned int spm_regulator_get_mode(struct regulator_dev *rdev)
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{
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struct spm_vreg *vreg = rdev_get_drvdata(rdev);
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return vreg->mode == QPNP_SMPS_MODE_PWM
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return vreg->mode == QPNP_LOGICAL_MODE_PWM
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? REGULATOR_MODE_NORMAL : REGULATOR_MODE_IDLE;
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}
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@ -480,8 +562,8 @@ static int spm_regulator_set_mode(struct regulator_dev *rdev, unsigned int mode)
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* in the case that qcom,mode has been specified as "pwm" in device
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* tree.
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*/
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vreg->mode
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= mode == REGULATOR_MODE_NORMAL ? QPNP_SMPS_MODE_PWM : vreg->init_mode;
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vreg->mode = (mode == REGULATOR_MODE_NORMAL) ? QPNP_LOGICAL_MODE_PWM
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: vreg->init_mode;
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return qpnp_smps_set_mode(vreg, vreg->mode);
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}
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@ -538,7 +620,7 @@ static int spm_regulator_avs_set_voltage(struct regulator_dev *rdev, int min_uV,
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return -EINVAL;
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}
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vlevel_max = (uV - range->min_uV) / range->step_uV;
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vlevel_max = spm_regulator_uv_to_vlevel(vreg, uV);
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avs_max_uV = spm_regulator_vlevel_to_uv(vreg, vlevel_max);
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if (avs_max_uV < min_uV) {
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@ -646,6 +728,9 @@ static int qpnp_smps_check_type(struct spm_vreg *vreg)
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} else if (type[0] == QPNP_FTS2p5_TYPE
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&& type[1] == QPNP_FTS2p5_SUBTYPE) {
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vreg->regulator_type = QPNP_TYPE_FTS2p5;
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} else if (type[0] == QPNP_FTS426_TYPE
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&& type[1] == QPNP_FTS426_SUBTYPE) {
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vreg->regulator_type = QPNP_TYPE_FTS426;
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} else if (type[0] == QPNP_ULT_HF_TYPE
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&& type[1] == QPNP_ULT_HF_SUBTYPE) {
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vreg->regulator_type = QPNP_TYPE_ULT_HF;
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@ -750,10 +835,10 @@ static int qpnp_smps_init_mode(struct spm_vreg *vreg)
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&mode_name);
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if (!rc) {
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if (strcmp("pwm", mode_name) == 0) {
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vreg->init_mode = QPNP_SMPS_MODE_PWM;
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vreg->init_mode = QPNP_LOGICAL_MODE_PWM;
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} else if ((strcmp("auto", mode_name) == 0) &&
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(vreg->regulator_type != QPNP_TYPE_ULT_HF)) {
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vreg->init_mode = QPNP_SMPS_MODE_AUTO;
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vreg->init_mode = QPNP_LOGICAL_MODE_AUTO;
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} else {
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dev_err(&vreg->pdev->dev,
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"%s: unknown regulator mode: %s\n",
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@ -761,13 +846,9 @@ static int qpnp_smps_init_mode(struct spm_vreg *vreg)
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return -EINVAL;
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}
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rc = regmap_write(vreg->regmap,
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vreg->spmi_base_addr + QPNP_SMPS_REG_MODE,
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*&vreg->init_mode);
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rc = qpnp_smps_set_mode(vreg, vreg->init_mode);
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if (rc)
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dev_err(&vreg->pdev->dev,
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"%s: could not write mode register, rc=%d\n",
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__func__, rc);
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return rc;
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} else {
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rc = regmap_read(vreg->regmap,
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vreg->spmi_base_addr + QPNP_SMPS_REG_MODE,
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@ -776,7 +857,7 @@ static int qpnp_smps_init_mode(struct spm_vreg *vreg)
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dev_err(&vreg->pdev->dev,
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"%s: could not read mode register, rc=%d\n",
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__func__, rc);
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vreg->init_mode = (u8)val;
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vreg->init_mode = qpnp_regval_to_mode(vreg, val);
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}
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vreg->mode = vreg->init_mode;
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@ -801,26 +882,41 @@ static int qpnp_smps_init_step_rate(struct spm_vreg *vreg)
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}
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reg = (u8)val;
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/* ULT buck does not support steps */
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if (vreg->regulator_type != QPNP_TYPE_ULT_HF)
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/* ULT and FTS426 bucks do not support steps */
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if (vreg->regulator_type != QPNP_TYPE_ULT_HF && vreg->regulator_type !=
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QPNP_TYPE_FTS426)
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step = (reg & QPNP_SMPS_STEP_CTRL_STEP_MASK)
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>> QPNP_SMPS_STEP_CTRL_STEP_SHIFT;
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delay = (reg & QPNP_SMPS_STEP_CTRL_DELAY_MASK)
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>> QPNP_SMPS_STEP_CTRL_DELAY_SHIFT;
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if (vreg->regulator_type == QPNP_TYPE_FTS426) {
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delay = (reg & QPNP_FTS426_STEP_CTRL_DELAY_MASK)
|
||||
>> QPNP_FTS426_STEP_CTRL_DELAY_SHIFT;
|
||||
|
||||
/* step_rate has units of uV/us. */
|
||||
vreg->step_rate = QPNP_SMPS_CLOCK_RATE * vreg->range->step_uV
|
||||
* (1 << step);
|
||||
/* step_rate has units of uV/us. */
|
||||
vreg->step_rate = QPNP_FTS426_CLOCK_RATE * vreg->range->step_uV;
|
||||
} else {
|
||||
delay = (reg & QPNP_SMPS_STEP_CTRL_DELAY_MASK)
|
||||
>> QPNP_SMPS_STEP_CTRL_DELAY_SHIFT;
|
||||
|
||||
/* step_rate has units of uV/us. */
|
||||
vreg->step_rate = QPNP_SMPS_CLOCK_RATE * vreg->range->step_uV
|
||||
* (1 << step);
|
||||
}
|
||||
|
||||
if ((vreg->regulator_type == QPNP_TYPE_ULT_HF)
|
||||
|| (vreg->regulator_type == QPNP_TYPE_HF))
|
||||
vreg->step_rate /= 1000 * (QPNP_HF_STEP_DELAY << delay);
|
||||
else if (vreg->regulator_type == QPNP_TYPE_FTS426)
|
||||
vreg->step_rate /= 1000 * (QPNP_FTS426_STEP_DELAY << delay);
|
||||
else
|
||||
vreg->step_rate /= 1000 * (QPNP_FTS2_STEP_DELAY << delay);
|
||||
|
||||
vreg->step_rate = vreg->step_rate * QPNP_FTS2_STEP_MARGIN_NUM
|
||||
/ QPNP_FTS2_STEP_MARGIN_DEN;
|
||||
if (vreg->regulator_type == QPNP_TYPE_FTS426)
|
||||
vreg->step_rate = vreg->step_rate * QPNP_FTS426_STEP_MARGIN_NUM
|
||||
/ QPNP_FTS426_STEP_MARGIN_DEN;
|
||||
else
|
||||
vreg->step_rate = vreg->step_rate * QPNP_FTS2_STEP_MARGIN_NUM
|
||||
/ QPNP_FTS2_STEP_MARGIN_DEN;
|
||||
|
||||
/* Ensure that the stepping rate is greater than 0. */
|
||||
vreg->step_rate = max(vreg->step_rate, 1);
|
||||
|
|
@ -831,7 +927,8 @@ static int qpnp_smps_init_step_rate(struct spm_vreg *vreg)
|
|||
static bool spm_regulator_using_range0(struct spm_vreg *vreg)
|
||||
{
|
||||
return vreg->range == &fts2_range0 || vreg->range == &fts2p5_range0
|
||||
|| vreg->range == &ult_hf_range0 || vreg->range == &hf_range0;
|
||||
|| vreg->range == &ult_hf_range0 || vreg->range == &hf_range0
|
||||
|| vreg->range == &fts426_range;
|
||||
}
|
||||
|
||||
/* Register a regulator to enable/disable AVS and set AVS min/max limits. */
|
||||
|
|
@ -969,6 +1066,8 @@ static int spm_regulator_probe(struct platform_device *pdev)
|
|||
rc = qpnp_smps_init_range(vreg, &fts2_range0, &fts2_range1);
|
||||
else if (vreg->regulator_type == QPNP_TYPE_FTS2p5)
|
||||
rc = qpnp_smps_init_range(vreg, &fts2p5_range0, &fts2p5_range1);
|
||||
else if (vreg->regulator_type == QPNP_TYPE_FTS426)
|
||||
vreg->range = &fts426_range;
|
||||
else if (vreg->regulator_type == QPNP_TYPE_HF)
|
||||
rc = qpnp_smps_init_range(vreg, &hf_range0, &hf_range1);
|
||||
else if (vreg->regulator_type == QPNP_TYPE_ULT_HF)
|
||||
|
|
@ -1050,8 +1149,8 @@ static int spm_regulator_probe(struct platform_device *pdev)
|
|||
vreg->rdesc.name,
|
||||
spm_regulator_using_range0(vreg) ? "LV" : "MV",
|
||||
vreg->uV,
|
||||
vreg->init_mode & QPNP_SMPS_MODE_PWM ? "PWM" :
|
||||
(vreg->init_mode & QPNP_SMPS_MODE_AUTO ? "AUTO" : "PFM"),
|
||||
vreg->init_mode == QPNP_LOGICAL_MODE_PWM ? "PWM" :
|
||||
(vreg->init_mode == QPNP_LOGICAL_MODE_AUTO ? "AUTO" : "PFM"),
|
||||
vreg->step_rate);
|
||||
|
||||
return rc;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue